A 0.5-V, 1.47- $\mu\hbox{W}$ 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

Ha, Hyunsoo; Lee, Seon-Kyoo; Kim, Byungsub; Park, Hong-June; Sim, Jae‐Yoon

doi:10.1109/tcsii.2014.2350378

Cited by 15 publications

(3 citation statements)

References 2 publications

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“…The work in reference [ 11 ] presents a low-power (~0.7 μW) SAR ADC for which calibration is performed off-chip. The work in [ 27 ] presents a 13-bit SAR ADC with on-chip calibration in a relatively large area of 0.9 mm 2 using 0.13 μm CMOS. Our work is realized using 0.18 μm CMOS in a compact chip area of 0.28 mm 2 .…”

Section: Measured Resultsmentioning

confidence: 99%

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Lee

Park

Cho

et al. 2018

Sensors

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Herein, we present an energy efficient successive-approximation-register (SAR) analog-to-digital converter (ADC) featuring on-chip dual calibration and various accuracy-enhancement techniques. The dual calibration technique is realized in an energy and area-efficient manner for comparator offset calibration (COC) and digital-to-analog converter (DAC) capacitor mismatch calibration. The calibration of common-mode (CM) dependent comparator offset is performed without using separate circuit blocks by reusing the DAC for generating calibration signals. The calibration of the DAC mismatch is efficiently performed by reusing the comparator for delay-based mismatch detection. For accuracy enhancement, we propose new circuit techniques for a comparator, a sampling switch, and a DAC capacitor. An improved dynamic latched comparator is proposed with kick-back suppression and CM dependent offset calibration. An accuracy-enhanced bootstrap sampling switch suppresses the leakage-induced error <180 μV and the sampling error <150 μV. The energy-efficient monotonic switching technique is effectively combined with thermometer coding, which reduces the settling error in the DAC. The ADC is realized using a 0.18 μm complementary metal–oxide–semiconductor (CMOS) process in an area of 0.28 mm2. At the sampling rate fS = 9 kS/s, the proposed ADC achieves a signal-to-noise and distortion ratio (SNDR) of 55.5 dB and a spurious-free dynamic range (SFDR) of 70.6 dB. The proposed dual calibration technique improves the SFDR by 12.7 dB. Consuming 1.15 μW at fS = 200 kS/s, the ADC achieves an SNDR of 55.9 dB and an SFDR of 60.3 dB with a figure-of-merit of 11.4 fJ/conversion-step.

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Section: Measured Resultsmentioning

confidence: 99%

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Lee

Park

Cho

et al. 2018

Sensors

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“…• To achieve power consumption in the nanowatt range, Wenbin et al proposed a SAR ADC for Wearable Medical Devices. 65 An ultra-low-power SAR ADC with a sampling rate of 40 Ks S −1 which is suitable for clinical laboratory biosensor was proposed by Hyunsoo Ha et al 66 Wen-Sin et al proposed a SAR ADC based on the binary search algorithm where the voltage signal is sampled before the conversion with an approximation of the selected MSB (Most Significant Bit). This type of ADC is suitable for bionic IMD 67 8-bit energyefficient SAR ADC based on a single-ended structure with bootstrapped switch to save power was proposed by E.Atkin et al 68 but it consumes power at the range of microwatt.…”

Section: Components In Biosensorsmentioning

confidence: 99%

Review—Power Approaches for Biosensors based Bio-Medical Devices

Gifta¹,

Rani²

2020

ECS J. Solid State Sci. Technol.

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Health care industries are progressing towards improving the health condition of the society, by developing new medical devices with innovative technologies. The advancement in medical technology has brought to reality developing sensor-based medical devices, which are implantable as well as wearable. The present challenge is designing in terms of low noise, low power, low area design techniques, considering patient safety and for a long term process these devices are getting more prevalent in the society. Addressing the problem of battery drain in Implantable Medical Devices (IMD) to the replacement of IMDs and additional surgeries would be the solution due to that. This survey paper presents a glimpse of a deep survey done on various types of power approaches that are carried out on Implantable Medical Devices focusing on extending their durability and attempts done to design various types of amplifiers and converters for sensors used in different medical devices.

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“…The capacitor mismatch is minimized by increasing the size of the capacitor; however, this slows down the conversion speed and unfortunately increases the chip area and power. A much better way to alleviate the capacitor mismatch issue is to perform capacitor mismatch calibration [2] [3]. On one hand, in very high sampling rate (200-500 MS/s) applications, medium-resolution SAR ADCs are increasingly used.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of 10 Bit, 2MS/s Split SAR ADC Using 0.18um CMOS Technology

Hosur¹,

Attimarad²,

Kittur³

2015

VLSICS

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This paper focuses on Design and Implementation of 10 Bit, 2MS/s successive approximation Register (SAR) Analog to digital converter (ADC) using Split DAC architecture. This SAR ADC architecture is designed and simulated using GPDK 0.18um CMOS technology. It consists of different blocks like sample and hold, comparator, Successive Approximation Register (SAR) and Split Digital to analog converter (DAC). For each block of SAR ADC power is calculated. DAC is an important component within the SAR ADC. The charge redistribution DAC in a Split capacitor configuration has a total capacitance which is 96.87% smaller compared to a conventional binary weighted design. Hence Split DAC gives an optimized architecture and it consumes less power. Optimized design of DAC architecture ensures the accuracy of the components, which improves the performance of SAR ADC. Comparator constructed from resistances, capacitance and dependent voltage sources instead of MOS transistors. Dynamic range for SAR ADC using split DAC is 60.19dB. The supply voltage is 1.2V. The total Power consumed by SAR ADC using Split array DAC is 95.65114uW and SAR ADC using binary weighted capacitor DAC is 211.19084uW.

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A 0.5-V, 1.47- $\mu\hbox{W}$ 40-kS/s 13-bit SAR ADC With Capacitor Error Compensation

Cited by 15 publications

References 2 publications

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

A 1.15 μW 200 kS/s 10-b Monotonic SAR ADC Using Dual On-Chip Calibrations and Accuracy Enhancement Techniques

Review—Power Approaches for Biosensors based Bio-Medical Devices

Design and Implementation of 10 Bit, 2MS/s Split SAR ADC Using 0.18um CMOS Technology

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