A 0.5 V, 1.2 mW, 160 fJ, 600 MS/s 5 bit Flash ADC

Miyahara, Masaya; Lin, James; Yoshihara, Kei; Matsuzawa, Akira

doi:10.1109/asscc.2010.5716584

Cited by 10 publications

(11 citation statements)

References 9 publications

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“…The leakage power of this ADC is approximately 0.76 mW at DC. This is caused by the use of low-threshold devices and forward body biasing [29] to maximize the speed of the ADC. Due to the dynamic residue amplifiers, the power consumption of this ADC is clock scalable as illustrated in Fig.…”

Section: Resultsmentioning

confidence: 99%

“…This technique is simple to realize in the proposed ADC as the sampling capacitors in the first stage and the residue amplifiers in the following stages readily provide the shifted signals ( in the first stage and and in the following stages) required for the gate-weighted interpolation. To compensate for the offset voltages of the dynamic comparators, a time-based offset calibration technique is employed [29]. This automatically tunes the activation clocks, and , of the two branches of a comparator to suppress the offset voltage.…”

Section: F Sub-adcmentioning

confidence: 99%

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An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Lin

Paik

Lee

et al. 2015

IEEE J. Solid-State Circuits

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This paper presents a 0.55 V, 7 bit, 160 MS/s pipeline ADC using dynamic amplifiers. In this ADC, high-speed open-loop dynamic amplifiers with a common-mode detection technique are used as residue amplifiers to increase the ADC's speed, to enhance the robustness against supply voltage scaling, and to realize clockscalable power consumption. To mitigate the absolute gain constraint of the residue amplifiers in a pipeline ADC, the interpolated pipeline architecture is employed to shift the gain requirement from absolute to relative accuracy. To show the new requirements of the residue amplifiers, the effects of gain mismatch and nonlinearity of the dynamic amplifiers are analyzed. The 7 bit prototype ADC fabricated in 90 nm CMOS demonstrates an ENOB of 6.0 bits at a conversion rate of 160 MS/s with an input close to the Nyquist frequency. At this conversion rate, it consumes 2.43 mW from a 0.55 V supply. The resulting FoM of the ADC is 240 fJ/conversion-step.

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Section: Resultsmentioning

confidence: 99%

Section: F Sub-adcmentioning

confidence: 99%

An Ultra-Low-Voltage 160 MS/s 7 Bit Interpolated Pipeline ADC Using Dynamic Amplifiers

Lin

Paik

Lee

et al. 2015

IEEE J. Solid-State Circuits

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“…In this paper, the research topic of ULV high-speed design for flash ADCs is explored [18], [21]. In Section II, the concept of the FD product proposed in [18] is further elaborated to include second-order effects; thus, this paper provides a more comprehensive explanation of the FD product.…”

Section: Introductionmentioning

confidence: 99%

“…Unfortunately, this issue is not reflected in the conventional figure of merit (FoM) as it focuses on energy efficiency [17]. As a result, a new index, the FoM-delay (FD) product, is introduced for ULV ADCs to clearly illustrate the tradeoff between the energy efficiency and the conversion speed [18].…”

Section: Introductionmentioning

confidence: 99%

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Ultralow-Voltage High-Speed Flash ADC Design Strategy Based on FoM-Delay Product

Lin

Mano

Miyahara

et al. 2015

IEEE Trans. VLSI Syst.

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This paper discusses the ultralow-voltage (ULV) design strategy for high-speed flash analog-to-digital converters (ADCs). A lower supply voltage decreases the energy consumption at the cost of conversion speed. In this paper, a new index, the figure-of-merit (FoM)-delay (FD) product, is introduced to provide a balance between the energy efficiency and conversion speed. As a prototype, a 0.5 V, 420-MS/s, and 7-bit, flash ADC is developed using a 90-nm CMOS technology to demonstrate the validity of ULV operation. To overcome the challenges associated with a reduced supply voltage, a double-tail latched comparator with a variable capacitance calibration technique using metal- oxide-metal capacitors is implemented. An all-digital timedomain delay interpolation technique further enhances the resolution with very little additional power consumption. Using twoway time-interleaving, the prototype ADC achieves an effective number of bits (ENOB) of 5.5 bitswhile operating at 420 MS/s consuming a total power of 4.1 mW. The lowest measured FoM is the 195 fJ/conv.-step during single-channel operation at 210 MS/s, which results in an extremely low FD product of 0.93 pJ × ns/conv.-step. Index Terms-Analog-to-digital converter (ADC), delay interpolation, figure-of-merit (FoM)-delay (FD) product, flash, high speed, ultralow voltage (ULV).

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