A 0.5–9.5-GHz, 1.2- $\mu \text{s}$ Lock-Time Fractional-N DPLL With ±1.25%UI Period Jitter in 16-nm CMOS for Dynamic Frequency and Core-Count Scaling

Ahmad, Fazil; Unruh, Greg; Iyer, Amrutha; Su, Pin-En; Abdalla, Sherif; Shen, Bo; Chambers, Mark; Fujimori, Ichiro

doi:10.1109/jssc.2016.2626338

Cited by 11 publications

(2 citation statements)

References 15 publications

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“…As shown in Figure 4, this is the timing diagram of the two-stage MMD switching the frequency division ratio at the modulus expansion boundary (3 to 4), where the state of the 2/3 frequency division unit is simplified with a binary representation, e.g., state [01,10 ]= [1,2]. When the control signal P 2 P 1 P 0 is changed from 011 to 100, the frequency division ratio is switched from 3 to 4 because M 1 =0 at this time will lead to abnormal frequency division ratio switching.…”

Section: Modulus Expansion Technologymentioning

confidence: 99%

“…An advanced system-on-chip (SoC) often consists of various parts and components, including wireless transceivers, memory, multi-core processors, I/O interfaces, and power management [1] . Each of these modules operates in a separate, unique clock domain, and these clock domains are distinct from one another [2] . Fractional-N phase-locked loop is an essential module in SOC.…”

Section: Introductionmentioning

confidence: 99%

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Design of a multi-modulus divider with a wide frequency dividing range and low power consumption

Zhao

Huang

2023

J. Phys.: Conf. Ser.

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A method of moduli expansion was presented to address the issue of wrongly altering the divider ratio at the boundary of the modulus expansion when multi-mode dividers (MMD) were utilized in fractional-N phase locked loops (PLLs). The multi-mode frequency divider was designed as the cascade of the 2/3 frequency dividers with an RS control terminal. Compared to traditional methods, only one OR gate is required for each modulus expansion, reducing the chip area. The 2/3 divider was designed using a True Single-Phase Clocked (TSPC) D-trigger structure, and each D-trigger uses a logic control technique with clearing and setting the number. An eight-stage multi-mode frequency divider with modulus expansion was developed using SMIC 55 nm CMOS technology. The simulation results demonstrated the large frequency divider range of the multi-mode frequency divider and its ability to carry out consistent switching operations over the 8–511 frequency divider range. The power consumption is 66.04W at a supply voltage of 1V, an input frequency of 2GHz, and an output frequency of 250MHz.

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Section: Modulus Expansion Technologymentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%