A 0.45-V 300-MHz 10T Flowthrough SRAM With Expanded write/ read Stability and Speed-Area-Wise Array for Sub-0.5-V Chips

Abstract

Capable of only solving the READ-stability issue, many 8T-10T static RAM (SRAM) cells require extra WRITE-assist circuits to achieve low supply voltage operation. This brief proposes a novel 10T SRAM cell and a hybrid-divided-block array to enhance the READ-and-WRITE stability while achieving a higher operating speed with a smaller area overhead for sub-0.5 V applications. A 16-Kb 128-row 10T flowthrough SRAM macro is fabricated using a 90-nm bulk-CMOS process. The 10T cell area is only 1.7 times the size of a 6T cell. The measured VDDmin for the 10T 16-Kb macro is 240 mV. The proposed 16-Kb macro can achieve 300-MHz random access operation at 0.45 V for a 0.5 V system platform.Index Terms-Flowthrough, low voltage, READ disturb, static random access memory (SRAM), WRITE margin (WM).

A Low Leakage 9T SRAM Cell With Improve Stability in Sub-Threshold Region for IoT Applications

“…Negative-coupling noise generated by bitlines (BL and BLB) affects the hold stored logic '1' node. This results in an improvement in hold stability during the floating period for unselected cells [27]. Thus, HS and WL signals facilitate cross-point write access mechanism for the unselected column which eliminates column half-select problem in LP9T SRAM cell.…”

Circuit optimization of 4T, 6T, 8T, 10T SRAM bitcells in 28nm UTBB FD-SOI technology using back-gate bias control

“…cost on area and lity is achieved by transistors. Some itcells [8,9]. The nalty, limitation in ity of soft error on of 6T/8T/10T e lower VDDmin igher speed on top n UTBB FD-SOI doped to modulate s [10].…”

A 0.7 V input output-capacitor-free digitally controlled low-dropout regulator with high current efficiency in 0.35 μm CMOS technology

“…1, an SoC system contains a wide variety of analog, digital, and mixed-signal circuits. In addition, many of these circuits have been proposed with an ultralow supply voltage of 0.5 V, such as filters [3], analog-to-digital converters (ADCs) [4], digital-toanalog converters (DACs) [5], phase-locked loops (PLLs) [6], static random-access memory (SRAM) [7,8] and up-/down-conversion mixers [9]. LDOs are especially preferred in these low-power applications because of low-noise characteristics, a smaller size, and less complexity when compared with switching converters.…”