A 0.4 V bulk-input pseudo amplifier in 90nm CMOS technology

Ahmadpour, A.

doi:10.1109/ddecs.2010.5491762

Cited by 1 publication

(1 citation statement)

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“…To further improve the differential gain, PMOS devices (M 5x , M 6x and M 7x , M 8x ) are added. This configuration is a cross-coupled cascode pair that adds a negative resistance to the output and boosts the differential DC gain [19]. In this structure, the gate inputs of transistors M 5x and M 6x are biased at zero due to the limitation of the power supply voltage.…”

Section: Main Amplifier Circuitmentioning

confidence: 99%

A 0.4 V Bulk-Driven Amplifier for Low-Power Data Converter Applications

Rezaei¹,

Ahmadpour²,

Moghaddasi³

2013

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This paper presents the design of an ultra low-voltage (ULV) pseudo operational transconductance amplifier (P-OTA) that is able to operate with a single supply voltage as low as 0.4 V. The proposed circuit is based on the bulk-driven technique and use of cross-coupled self-cascode pairs that boosts the differential DC gain. The stability condition of this structure for the DC gain is considered by definition of two coefficients to cancel out a controllable percentage of the denominator. This expression for stability condition yield optimized value for the DC gain. Also, as the principle of operation of the proposed technique relies on matching conditions, Monte Carlo analyzes are considered to study of the behavior of the proposed circuit against mismatches. The designed P-OTA have a DC gain of 64 dB, 212 KHz unity gain bandwidth, 57phase margin that is loaded by 10 pF differential capacitive loads, while consume only 16 μW. Eventually, from the proposed P-OTA, a low-power Sample and Hold (S/H) circuit with sampling frequency of 10 KS/s has been designed and simulated. The correct functionality for this configuration is verified from –30℃ to 70℃. The simulated data presented is obtained using the HSPICE Environment and is valid for the 90 nm triple-well CMOS process.