A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems

Lukas, Christopher J.; Calhoun, Benton H.

doi:10.1109/iscas.2015.7169283

Cited by 4 publications

(2 citation statements)

References 15 publications

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“…Thus, if a stand-alone sensor is being developed, the digital interface can be customized to reduce power. Reducing the operating voltage of the digital interface between chips on a board reduces the power and energy dramatically at the cost of throughput [15]. This voltage can be tuned for the required sensor throughput enabling the application to reach its minimum energy and power consumption.…”

Section: Sensing Interfacesmentioning

confidence: 99%

A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things

Yahya

Lukas

Calhoun

2018

JLPEA

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This paper presents a top-down methodology for designing battery-less systems for the Internet-of-Things (IoT). We start by extracting features from a target IoT application and the environment in which it will be deployed. We then present strategies to translate these features into design choices that optimize the system and improve its reliability. We look into how to use these features to build the digital subsystem by determining the blocks to implement, the digital architecture, the clock rate of the system, the memory capacity, and the low power states. We also review how these features impact the choice of energy harvesting power management units.

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Section: Sensing Interfacesmentioning

confidence: 99%

A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things

Yahya

Lukas

Calhoun

2018

JLPEA

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“…Therefore, it is necessary to reduce the energy consumption of the digital chip-to-chip interface. Existing low-power wireline interfaces [3], [4] use smart supplies to further improve the energy efficiency. However, the achievable efficiency depends on the operating frequency and the maximum efficiency point is only possible with an ultralow supply voltage (0.24 V) and low data rate (<1 kb/s).…”

Section: Introductionmentioning

confidence: 99%

A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface With Data Rate and Load Capacitance Adaptability

Shen

Cantatore

et al. 2020

IEEE Solid-State Circuits Lett.

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A 3.77 nW, 11.4 fJ/b/mm link for reliable wireline communication in ultra-low power on-body sensor networks

Lukas

Calhoun

Bhakta

2017

2017 IEEE Biomedical Circuits and Systems Conference (BioCAS)

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A 0.38 pj/bit 1.24 nW chip-to-chip serial link for ultra-low power systems

Cited by 4 publications

References 15 publications

A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things

A Top-Down Approach to Building Battery-Less Self-Powered Systems for the Internet-of-Things

A 0.38-pJ/b Simplex and a 1.2-pJ/b Full-Duplex Chip-to-Chip Digital Communication Interface With Data Rate and Load Capacitance Adaptability

A 3.77 nW, 11.4 fJ/b/mm link for reliable wireline communication in ultra-low power on-body sensor networks

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