A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI

Biswas, Avishek; Chandrakasan, Anantha P.

doi:10.1109/esscirc.2016.7598334

Cited by 10 publications

(8 citation statements)

References 6 publications

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“…The array standby power (cell leakage) of this work is the lowest. When comparing [15] to [10], the E/access is double for a memory capacity that is twice as large. Hence, to take memory capacity into account, the E/bitcell metric is introduced, which shows similar performance in both implementations as well as [12].…”

Section: Performance Resultsmentioning

confidence: 99%

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

Vanhoof

Dehaene

2022

IEEE Solid-State Circuits Lett.

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This work presents a novel low leakage SRAM architecture with always-retention and local wake-up. To tackle the large design margins in deep sub-micron technology nodes, it includes SNM monitoring and compensation circuitry to track variation across the memory array. This allows for operation close to the point of first failure. As proof of concept, a macro of 1Mbit is fabricated in 22nm FDSOI. Measurements show an active energy of 3.6 pJ/access at 6.6 MHz and a leakage power of 0.19 pW/cell, a reduction of 53.8% due to margin reduction.

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Section: Performance Resultsmentioning

confidence: 99%

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

Vanhoof

Dehaene

2022

IEEE Solid-State Circuits Lett.

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“…Hence, in future work, data-dependent memory architectures e.g. 8T SRAMs, [23], [24] can be used to store and access the inputs/outputs. [23], [24] take advantage of data properties to significantly reduce memoryaccess energy, which would be highly useful here.…”

Section: Metricmentioning

confidence: 99%

“…8T SRAMs, [23], [24] can be used to store and access the inputs/outputs. [23], [24] take advantage of data properties to significantly reduce memoryaccess energy, which would be highly useful here. Compared to [5], [9], we achieve > 27× improvement in energy-efficiency, due to the massively parallel in-memory analog computations.…”

Section: Metricmentioning

confidence: 99%

CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

Biswas

Chandrakasan

2019

IEEE J. Solid-State Circuits

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283

142

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This work presents an energy-efficient SRAM with embedded dot-product computation capability, for binary-weight convolutional neural networks. A 10T bit-cell based SRAM array is used to store the 1-b filter weights. The array implements dotproduct as a weighted average of the bit-line voltages, which are proportional to the digital input values. Local integrating ADCs compute the digital convolution outputs, corresponding to each filter. We have successfully demonstrated functionality (> 98% accuracy) with the 10,000 test images in the MNIST handwritten digit recognition dataset, using 6-b inputs/outputs. Compared to conventional full-digital implementations using small bit-widths, we achieve similar or better energy-efficiency, by reducing data transfer, due to the highly parallel in-memory analog computations.

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“…DRAM vs SRAM). The cell size of a typical SRAM cell in a state of the art 28 nm technology is in the order of 200F 2 [49][50][51][52]. For the recent 14 and 16 nm technology nodes with more complicated transistor layouts such as tri-gate or FinFET, the cell sizes are even higher [49,53,54].…”

Section: Static and Dynamic Random Access Memory (Sram/dram)mentioning

confidence: 99%

Memory technology—a primer for material scientists

et al. 2020

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From our own experience, we know that there is a gap to bridge between the scientists focused on basic material research and their counterparts in a close-to-application community focused on identifying and solving final technological and engineering challenges. In this review, we try to provide an easy-to-grasp introduction to the field of memory technology for materials scientists. An understanding of the big picture is vital, so we first provide an overview of the development and architecture of memories as part of a computer and call attention to some basic limitations that all memories are subject to. As any new technology has to compete with mature existing solutions on the market, today's mainstream memories are explained, and the need for future solutions is highlighted. The most prominent contenders in the field of emerging memories are introduced and major challenges on their way to commercialization are elucidated. Based on these discussions, we derive some predictions for the memory market to conclude the paper.

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A 0.36V 128Kb 6T SRAM with energy-efficient dynamic body-biasing and output data prediction in 28nm FDSOI

Cited by 10 publications

References 6 publications

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

SRAM With Stability Monitoring and Body Bias Tuning for Biomedical Applications

CONV-SRAM: An Energy-Efficient SRAM With In-Memory Dot-Product Computation for Low-Power Convolutional Neural Networks

Memory technology—a primer for material scientists

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