A 0.22 nJ/b/iter 0.13 &amp;#x003BC;m turbo decoder chip using inter-block permutation interleaver

Wong, Cheng-Chi; Tang, Cheng-Hao; Lai, Ming-Wei; Zheng, Yu; Lin, Chien-Ching; Chang, Hsie-Chia; Lee, Chen‐Yi; Su, Yu T.

doi:10.1109/cicc.2007.4405731

Cited by 4 publications

References 8 publications

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A 50Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange

Kim

Park

2008

2008 IEEE Asian Solid-State Circuits Conference

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Abstract-A 50Mbps, 2.24mm 2 double-binary turbo decoder is designed and implemented in 0.13μm CMOS process for the WiMAX standard. To reduce the large extrinsic memory needed in double-binary turbo decoding, the proposed decoder exchanges the bit-level extrinsic information values rather than the traditional symbol-level extrinsic information values, which is achieved by deriving two simple conversions. The proposed turbo decoder, with a low-complexity hardware interleaver generating interleaved addresses for two data flows simultaneously, provides an efficient stopping criterion for double-binary turbo decoding using bit-level extrinsic information as well as huge memory size reduction of 20.6%.

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A 50Mbps double-binary turbo decoder for WiMAX based on bit-level extrinsic information exchange

Kim

Park

2008

2008 IEEE Asian Solid-State Circuits Conference

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Extrinsic data compression method for double-binary turbo codes

Ou-Yang

Kao

Hsu

et al. 2012

2012 IEEE International Symposium on Circuits and Systems

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This paper presents an extrinsic data compression method for double-binary turbo codes. Frame and extrinsic data memory occupy more area in turbo decoder implementations with the frame size increasing. Besides, non-binary turbo codes have much more extrinsic memory usage than single-binary turbo codes. This proposed compression method utilizes an operation in radix-4 single-binary turbo decoder and also can simplify the integration of single and double-binary turbo decoders in hardware implementations. It can reduce one-third of extrinsic memory size, about 15% of total memory usage. Simulation results show that this method only causes 0.2dB performance loss when bit error rate is equal to 10 -5 with slight hardware increment.

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