A 0.2-V 30-MS/s 11b-ENOB Open-Loop VCO-Based ADC in 28-nm CMOS

Abstract

We present a 0.2-V open-loop voltage-controlled oscillator (VCO)-based analog-to-digital converter (ADC) intended for IoT wireless sensor nodes. A resistor-based frequency-tuning scheme helps in mitigating odd-order harmonic distortion induced by the VCO nonlinear transfer characteristic. It also provides a reconfigurable input range, allowing it to exceed the supply by 2.5× (single-ended), and maintaining tolerance against ±10% supply variations. Latch, flip-flops, and logic gates within the frequency-to-digital converter are designed for minimum propagation delays, allowing sampling at 30 MS/s. The ADC is implemented in 28-nm CMOS and achieves a peak SNDR of 68 dB, equivalent to an ENOB of 11, over a 61-kHz bandwidth with a 1-V pp input differential sinewave. It consumes 7 µW, resulting in a state-of-the-art Walden and Schreier FoM of 27.8 fJ/c-s and 167.4 dB, respectively.

The Analog Behavior of Pseudo Digital Ring Oscillators Used in VCO ADCs

“…Consequently, the overall falling edge delay τ d f and the overall rising edge delay τ dr are obtained by the averaging Eqs. (15,16) as well, but this time substituting Eq. (19) and the equivalent expressions for τ dr+ and the negative half cell delays.…”

“…(20) and taking into account the balancing effect due to the differential nature, see Eqs. (15,16), a similar noise calculation can be done for the direct cross-coupled VCO delay cell:…”

“…Linearity issues in VCO ADCs can be tackled by the use of a pseudo-differential setup [3] and by employing proper architectural techniques such as two-stage [4], [5] or feedback based architectures [6]- [12], etc. Circuit-level improvements also exist in prior art [13]- [15] and as a last resort, digital calibration [16]- [20] can be used. In this work we will not address linearity any further.…”

Time-Encoding Analog-to-Digital Converters: Bridging the Analog Gap to Advanced Digital CMOS?Part 2: Architectures and Circuits

“…11(a) (the figure shows the bottom drive version), originally proposed in [48]. Various implementations [10], [48]- [50] have demonstrated up to 11 bits of linearity in a pseudo-differential VCO-based ADC.…”

Dickson-Charge-Pump-Based Voltage-to-Time Conversion for Time-Based ADCs in 28-nm CMOS

“…The clock's phase is then sampled and differentiated such that the ADC's digital output is ideally proportional to the analog input. Unfortunately, the nonlinearity of the VCO's voltage-to-frequency conversion, which originates from the active devices, will directly affect the ADC's nonlinearity, thus requiring extensive calibration due to PVT variations [3].…”