A 0.18 pJ/Step Time-Domain 1st Order ΔΣ Capacitance-to-Digital Converter in 65-nm CMOS

Abstract

This work presents a capacitance-to-digital converter (CDC) fully designed using time-domain circuits following the principle of a dual quantization based first-order ∆Σ modulator. The prototype supports capacitance measurement within the range of 0-3.75 pF and is implemented using a 65-nm CMOS Technology. It consumes 2 mW from a 1.2 V supply while sampling at a 100 MHz clock frequency. The CDC prototype achieves an ENOB of 12.9 bits with an energy efficiency of 0.18 pJ energy per conversion-step.Index Terms-Capacitance-to-digital converter (CDC), Timedomain integrator, delay-locked-loop (DLL), Time-domain Delta-Sigma Modulator 40 65 180 180 180 160 Method Time + Voltage Time + Voltage Time Voltage Voltage Voltage Time