A 0.18- $\mu \text{m}$ CMOS Image Sensor With Phase-Delay-Counting and Oversampling Dual-Slope Integrating Column ADCs Achieving $1{\text {e}}^{-}_{\mathrm{ rms}}$ Noise at 3.8- $\mu \text{s}$ Conversion Time

A 16‐bit Hybrid ADC with Circular‐Adder‐Based Counting for 15μm Pitch 640×512 LWIR FPAs

“…In addition, as both of them output analog signals at the pixel level, the charge-handling capacity of the pixel is limited by the capacitance. Pixel-level ADC has been widely adopted owing to its pixel-level digital output and low sampling rate, but its higher integration results in more hardware consumption, resulting in larger pixel pitch [8,9] .…”