A 0.13-$\mu$m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

Ha, Kwang Soon; Kim, Lee-Sup; Bae, Seung-Jun; Park, Kwang-Il; Choi, Jongwan; Jun, Young-Hyun; Kim, Kinam

doi:10.1109/jssc.2009.2031527

Cited by 19 publications

(12 citation statements)

References 17 publications

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“…3 shows the energy per bit as bandwidth is increased for MRF-I versus a traditional interconnect, which is labeled as baseband (BB). The power numbers for the baseband were taken [10], [14], [20]. We compare BB against 2ASK, 4ASK, and 8ASK.…”

Section: B Overhead Of Using Mrf-imentioning

confidence: 99%

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Therdsteerasukdi

Byun

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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Abstract-The demand for capacity and off-chip bandwidth to dynamic random-access memory (DRAM) will continue to grow as we integrate more cores onto a die. However, as the data rate of DRAM has increased, the number of dual in-line memory modules (DIMMs) supported on a multi-drop bus has decreased. Therefore, traditional memory systems are not sufficient to meet both these demands. We propose the DIMM tree architecture for better scalability by connecting the DIMMs as a tree. The DIMM tree architecture is able to grow the number of DIMMs exponentially with each level of latency in the tree. We also propose application of multiband radio-frequency interconnect (MRF-I) to the DIMM tree architecture for even greater scalability and higher throughput. The DIMM tree architecture without MRF-I was able to scale up to 64 DIMMs with only an 8% degradation in throughput over an ideal system. The DIMM tree architecture with MRF-I was able to increase throughput by 68% (up to 200%) on a 64-DIMM system over a 4-DIMM system. Finally, we propose the partitioned DIMM tree, which allows the scaling of a main memory system to a many-DIMM memory system while still maintaining high throughput. The partitioned DIMM tree is able to improve throughput by an average of 19% up to 35% over the DIMM tree with 256 DIMMs on a single channel.Index Terms-Integrated circuit interconnections, memory architecture, radio-frequency integrated circuits, random access memory.

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Section: B Overhead Of Using Mrf-imentioning

confidence: 99%

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Therdsteerasukdi

Byun

et al. 2012

IEEE J. Emerg. Sel. Topics Circuits Syst.

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“…However, reference signal (V ref ) noise reduces the noise margin of receiver input signals [1]. Several works are reported to solve the problems owing to reference signal noise [1][2][3][4]. However, in [1,2], simultaneous switching noise (SSN) is not completely removed and a reference voltage offset also exists.…”

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confidence: 99%

“…In [3], it is difficult to increase the number of parallel data because of the complexity of encoders. The pseudo-differential signalling (PDS) in [4] removes the common-mode noise owing to SSN. However, since the receiver in [4] uses three-level signals with common level and the three-level signals are vulnerable to core power noise, it needs many decoupling capacitors for stable core power.…”

mentioning

confidence: 99%

“…The pseudo-differential signalling (PDS) in [4] removes the common-mode noise owing to SSN. However, since the receiver in [4] uses three-level signals with common level and the three-level signals are vulnerable to core power noise, it needs many decoupling capacitors for stable core power. In this Letter we propose a receiver which is robust to core power noise in PDS.…”

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confidence: 99%

“…1 shows the proposed receiver and its operation waveforms. The receiver detects pseudo-differential signals using 'Transition [(0,1), (1,0)]' and 'No transition [(0,0), (1,1)]' relation in PDS [4]. The receiver consists of a threelevel differential buffer (TLDB), two comparators and a symmetric XOR which does not induce the jitter due to the variation of input signal patterns [5].…”

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confidence: 99%

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Three-level differential buffer for increasing noise margin in pseudo-differential signalling

Kim

Bae

et al. 2010

Electron. Lett.

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A 5Gbit/s/pin transceiver for high-speed memory interfaces is implemented in a 0.18 mm CMOS process. In general, memory interfaces use single-ended signalling with a reference signal because the chip cost is closely related to the number of pins. However, as the data rate increases, reference voltage noise and simultaneous switching noise reduce voltage and timing margin of receiver input signals. Pseudo-differential signalling (PDS) is used to solve the problems, however a previous receiver using PDS is sensitive to core power noise because the receiver uses three-level signals with reduced noise margin. The three-level differential buffer (TLDB) which is robust to core power noise is proposed and the noise margin of the TLDB outputs is larger than that of outputs of a previous PDS receiver.

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A 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers

et al. 2020

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This paper presents a 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers. To reduce size overhead from the dual‐mode interfaces, we propose the termination circuit that shares 50‐Ω terminations and common‐mode capacitors while maintaining a perfectly matched load balance. The proposed dual‐mode receiver can support 14‐Gb/s total bandwidth in each interface mode, resulting in broad compatibility with application processors. A mobile display driver using the proposed dual‐mode receiver is fabricated in a 28‐nm high‐voltage CMOS process and verified up to 3.5 Gb/s per lane in the D‐PHY mode and 2.2 Gs/s per trio in the C‐PHY.

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A 0.13-$\mu$m CMOS 6 Gb/s/pin Memory Transceiver Using Pseudo-Differential Signaling for Removing Common-Mode Noise Due to SSN

Cited by 19 publications

References 17 publications

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Utilizing Radio-Frequency Interconnect for a Many-DIMM DRAM System

Three-level differential buffer for increasing noise margin in pseudo-differential signalling

A 14‐Gb/s dual‐mode receiver with MIPI D‐PHY and C‐PHY interfaces for mobile display drivers

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