A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM

Andò,; Okazawa,; Furuta,; Ohkaaa,; Monden,; Kodama,; are,; Ishihara,; Sasaki, Mitsuru

doi:10.1109/vlsic.1988.1037418

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A 0.1/spl mu/A standby current, bouncing-noise-immune 1Mb SRAM

Cited by 16 publications

References 4 publications

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A stacked-CMOS cell technology for high-density SRAM's

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