A 0.0129 mm<sup>2</sup> DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

Luo, Zirong; Wang, Guoxing; Yousef, Khalil; Lau, Benjamin; Lian, Yong; Heng, Chun-Huat

doi:10.1109/tcsii.2018.2873619

Cited by 4 publications

(3 citation statements)

References 14 publications

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“…Additionally, since this locking step primarily controlled by the SIGN signal generated by a conventional phase detector, the robustness of the controller is further improved against process variation as compared to the conventional time-to-digital converter (TDC) based controller, which makes them sensitive to the any changes in resolution. The Figure-of-Merit for jitter (FOM jitter ) of the DAC-based and controller-based DCO outperform [8], and they are almost the same with [9]. The [10] is based on the schematic simulation, hence the FOM jitter is better than the proposed designs.…”

Section: Layout and Simulation Resultsmentioning

confidence: 90%

“…However, its active area is much larger than the proposed DAC-based and controller-based DCO in spite of the DCO that was implemented in 28 nm. The DAC-based DCO and controller-based DCO outperform [8,9] in terms of peak-to-peak jitter performance. The proposed design uses a simple architecture and it occupies a less active area.…”

Section: Layout and Simulation Resultsmentioning

confidence: 96%

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Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

2021

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This paper presents a comparative study between two different implementations of digitally-controlled-oscillators (DCOs), whcih is the DAC-based and the digital controller-based DCO in TSMC 65 nm CMOS technology. This paper focuses on ring-oscillator architectures due to their high stability against PVT. The DAC-based oscillator implements a differential architecture, and the digital controller-based architecture operates in a single-ended signal. The SFDR of the DAC-based DCO is 77.2 dBc and controller-based DCO is 56.8 dBc at 125 MHz offset. The Monte-Carlo simulation gives a deviation of 7.4% and 8.5% for the DAC-based and controller-based DCO, respectively. The phase noise performance of the DAC-based DCO and controller-based DCO is −78.9 dBc/Hz and −81.3 dBc/Hz at 1 MHz offset, respectively. The implementations are given and compared according to their performance based on post-layout simulation results.

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Section: Layout and Simulation Resultsmentioning

confidence: 90%

Section: Layout and Simulation Resultsmentioning

confidence: 96%

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

2021

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“…low K DCO ) by setting a small ratio of N 2 2 /(1+N 2 1 +N 2 2 ). The very fine K DCO helps with reducing the quantization noise of ADPLL in order to avoid a power hungry Σ∆ modulator [2], [9].…”

Section: Three-winding Resonator Designmentioning

confidence: 99%

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

Yuan

Lin

et al. 2020

IEEE Trans. Circuits Syst. II

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In this brief, we introduce a 3.2-4 GHz threewinding transformer-based class-F digitally controlled oscillator (DCO) with a DC-DC booster for energy harvesting applications. A π-model is adopted for this multi-turn transformer to analyze its impedance transformation and overall loop gain. The trifilar coil generates large passive voltage loop gain, allowing the DCO supply voltage of 0.2 V to be even lower than the threshold voltage of transistors without any performance degradation. Due to the gate/drain isolation as well as smaller voltage-dependent capacitance in advanced FinFET technology, this work achieves very low supply frequency pushing of 38 MHz/V. The switched capacitor placed at the tertiary winding can reach very fine resolution of 1.3 kHz due to the impedance transformations and source degeneration. The bias and control voltages of nearly zero power are generated with a switched-capacitor based DC-DC converter and a ring-based non-overlapped clock generator.

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Low phase noise, high resolution digitally-controlled ring oscillator operating at 2.2GHz

Selvaraj

Bayram

Negra

2020

2020 9th International Conference on Modern Circuits and Systems Technologies (MOCAST)

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A 0.0129 mm² DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

Cited by 4 publications

References 14 publications

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

Low phase noise, high resolution digitally-controlled ring oscillator operating at 2.2GHz

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A 0.0129 mm2 DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS

Cited by 4 publications

References 14 publications

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

Comparison of System-Level Design Approaches on Different Types of Digitally-Controlled Ring-Oscillator

A 0.2-V Three-Winding Transformer-Based DCO in 16-nm FinFET CMOS

Low phase noise, high resolution digitally-controlled ring oscillator operating at 2.2GHz

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Product

Resources

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A 0.0129 mm² DPLL With 1.6~2.0 ps RMS Period Jitter and 0.25-to-2.7 GHz Tunable DCO Frequency Range in 55-nm CMOS