A 0.0046-mm<sup>2</sup> Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation

Wendler, Daniel; Dorigo, Daniel De; Amayreh, Mohammad; Bleitner, Alexander; Marx, Maximilian; Willaredt, Roman; Manoli, Yiannos

doi:10.1109/jssc.2022.3190446

Cited by 18 publications

(24 citation statements)

References 42 publications

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“…Compared to the IA+ADC architecture described in [27], this work achieves a lower area of 0.225 mm 2 and power consumption of 17.1 µW. In contrast to the ∆Σ ADC structure shown in [28], this paper realizes a higher input range and SNDR. While similar to [29] in terms of power consumption and SNDR, this work has managed to achieve an input range of 500 mV pp by adjusting the feedback coefficients.…”

Section: Measurement Resultsmentioning

confidence: 98%

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

Liu,

Hou,

Wang

et al. 2024

Electronics

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This paper proposes a VCO-based ADC with first-order noise shaping for EEG signal recording front ends. Addressing the challenge of applying analog integrators in advanced processes due to low voltage issues, a multi-phase quantizer structure is introduced based on V-F conversion within the VCO structure, resulting in lower analog power consumption at the same output bit-width. By introducing a form of Gray code encoding, errors caused by circuit metastability are limited to within 1 bit. Considering the effects of motion artifacts and the electrode DC offset, the circuit achieves a wide input range of 500 mVpp by adjusting the feedback coefficients. A prototype ADC is fabricated using 180 nm CMOS technology, operating at a 1.8 V/1 V power supply voltage, with power consumption of 17.1 μW, while achieving a 62.1 dB signal-to-noise and distortion ratio (SNDR) and 55.2 dB dynamic range (DR). The proposed ADC exhibits input noise of 8.64 μVrms within a bandwidth of 0.5 Hz–5 kHz.

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Section: Measurement Resultsmentioning

confidence: 98%

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

Liu,

Hou,

Wang

et al. 2024

Electronics

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“…Researchers at the University of Freiburg presented a technological solution for the incorporation of digitalization electronics within the shank (rather than on the base) of active CMOS probes. In this case, Analog-to-Digital Converter (ADC) circuits were directly integrated beneath each electrode site (De Dorigo et al, 2018;Wendler et al, 2023). Moving the whole signal conditioning and acquisition circuits in the probe shank allows to significantly reduce the dimensions of the base and the total number of required interconnection wires (minimum of 7).…”

Section: Active Cmos Technology and Its Advantagesmentioning

confidence: 99%

“…Both studies highlight a stricter constraint on the power consumption of the probe shank compared to the base, potentially due to its high aspect ratio and due to it being in direct contact with brain tissue. This observation is particularly relevant for the design of active CMOS probes aiming to implement the whole signal processing chain in the shank of the probe (De Dorigo et al, 2018;Wendler et al, 2023), where it is most critical to assess and constrain power consumption to avoid excessive heating.…”

Section: Active Cmos Technology and Its Advantagesmentioning

confidence: 99%

“…The feasibility of interfacing active silicon probes with flexible polyimide interconnects to mechanically decouple stiff probes from the skull was proved by Barz et al (2020). A different approach for achieving flexible interconnection of active CMOS probes with external electronics was presented by De Dorigo et al ( 2018) and Wendler et al (2023), who produced active probes with ADC circuits directly integrated in the probe shank rather than in the base. This strategy allows to reduce the required number of interconnection wires down to 7 and to shrink base dimensions, allowing to achieve free-floating probes with a high potential in applications involving subcortical deep brain regions.…”

Section: Active Cmos Technology and Its Advantagesmentioning

confidence: 99%

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Advancing the interfacing performances of chronically implantable neural probes in the era of CMOS neuroelectronics

Perna,

Angotzi,

Berdondini

et al. 2023

Front. Neurosci.

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Tissue penetrating microelectrode neural probes can record electrophysiological brain signals at resolutions down to single neurons, making them invaluable tools for neuroscience research and Brain-Computer-Interfaces (BCIs). The known gradual decrease of their electrical interfacing performances in chronic settings, however, remains a major challenge. A key factor leading to such decay is Foreign Body Reaction (FBR), which is the cascade of biological responses that occurs in the brain in the presence of a tissue damaging artificial device. Interestingly, the recent adoption of Complementary Metal Oxide Semiconductor (CMOS) technology to realize implantable neural probes capable of monitoring hundreds to thousands of neurons simultaneously, may open new opportunities to face the FBR challenge. Indeed, this shift from passive Micro Electro-Mechanical Systems (MEMS) to active CMOS neural probe technologies creates important, yet unexplored, opportunities to tune probe features such as the mechanical properties of the probe, its layout, size, and surface physicochemical properties, to minimize tissue damage and consequently FBR. Here, we will first review relevant literature on FBR to provide a better understanding of the processes and sources underlying this tissue response. Methods to assess FBR will be described, including conventional approaches based on the imaging of biomarkers, and more recent transcriptomics technologies. Then, we will consider emerging opportunities offered by the features of CMOS probes. Finally, we will describe a prototypical neural probe that may meet the needs for advancing clinical BCIs, and we propose axial insertion force as a potential metric to assess the influence of probe features on acute tissue damage and to control the implantation procedure to minimize iatrogenic injury and subsequent FBR.

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“…However, due to its complex signal chain, recording chips that employ this architecture often require significant power consumption and area. The second architecture of recording chips omits the low noise amplifiers and directly quantizes neural signals using a low noise ADC [20,21,22,23,24,25,26,27,28,29,30]. Due to its simplified signal processing chain, this architecture can often achieve a low single-channel area [23,24,25,26,27], or a large input range with low power consumption [28,29,30], making it highly promising for future research.…”

Section: Introductionmentioning

confidence: 99%

A 16-µW 10-kHz BW incremental <i>ΔΣ</i> ADC with automatic EDO canceling for implantable neural recording

Zhang,

Liu,

Yang

et al. 2024

IEICE Electron. Express

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This paper presents a DC-coupled, incremental ΔΣ analog-to-digital converter (ADC) based on two-step quantization for high-density implantable neural signal recording. To address the problem of electrode DC offset (EDO), a compensation circuit is proposed in this paper which can automatically cancel the EDO. Fabricated in a 180-nm CMOS process, the prototype ADC achieves a high input impedance, 20-mVpp linear input range, 60.3-dB signal-to-noise and distortion ratio (SNDR). Its core circuit has a power consumption of 16 𝜇W and an area of 0.0165𝑚𝑚 2 .The referedto-input (RTI) noise is 6 𝜇Vrms (1-10kHz) and it can cancel the EDO up to ±90𝑚𝑉 .

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A 0.0046-mm² Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation

Cited by 18 publications

References 42 publications

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

Advancing the interfacing performances of chronically implantable neural probes in the era of CMOS neuroelectronics

A 16-µW 10-kHz BW incremental <i>ΔΣ</i> ADC with automatic EDO canceling for implantable neural recording

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A 0.0046-mm2 Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation

Cited by 18 publications

References 42 publications

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

A 500 mVpp Input Range First-Order VCO-Based ADC with a Multi-Phase Quantizer for EEG Recording Front Ends

Advancing the interfacing performances of chronically implantable neural probes in the era of CMOS neuroelectronics

A 16-µW 10-kHz BW incremental <i>ΔΣ</i> ADC with automatic EDO canceling for implantable neural recording

Contact Info

Product

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A 0.0046-mm² Two-Step Incremental Delta–Sigma Analog-to-Digital Converter Neuronal Recording Front End With 120-mVpp Offset Compensation