A 0.003 mm<sup>2</sup>5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE

Boesch, Ryan; Zheng, Kevin; Murmann, Boris

doi:10.1109/vlsic.2016.7573522

Cited by 7 publications

(3 citation statements)

References 5 publications

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“…The circuit is inverter-based. An inverter and a diode-connected inverter form a basic inverting amplifier unit [26,27,28,29,30,31]. The basic inverting amplifier unit is shown in Fig.…”

Section: Common-mode Voltage Stabilization Circuitmentioning

confidence: 99%

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Han

Wang

2021

IEICE Electron. Express

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This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate receiver based on amplitude rectification. Compared with the conventional three-comparator structure, the PAM4 signal is converted into a 2-digit gray-code rather than a 3-digit thermometer-code. The amplitude is detected to decode the least significant bit (LSB), which allows the proposed receiver to use significantly less power by reducing the number of comparators. An inverter-based common-mode voltage stabilization circuit (CVSC) is proposed to reduce the effect of common-mode level changes as the amplitude is determined. To minimize the feedback delay, the 2-digit gray-code is fed back to DFE's summer directly. By reducing the digit of the feedback signal, the power will be further reduced as the DFE tap increases. The device consumes 83.5 mW over a 55-nm process.

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“…The circuit is inverter-based. An inverter and a diode-connected inverter form a basic inverting amplifier unit [26,27,28,29,30,31]. The basic inverting amplifier unit is shown in Fig.…”

Section: Common-mode Voltage Stabilization Circuitmentioning

confidence: 99%

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Han

Wang

2021

IEICE Electron. Express

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“…However, it could also be used in combination with systems still using limited DSP where the channel equalization is removed from the DSP. This will yield a reduction in latency, power reduction in the DSP and requires a smaller dynamic range and resolution in the used ADCs [15]- [17]. From this point on, a single polarization link is assumed in the discussion and hence only a single channel equalizer is considered.…”

Section: Analog Coherent Transmission Systemmentioning

confidence: 99%

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

Verplaetse

Lambrecht

Vanhoecke

et al. 2020

IEEE J. Solid-State Circuits

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We propose a novel implementation of a complex analog equalization filter for the compensation of frequency dependent variations in coherent optical links. The analog compensation filter can be used in coherent-lite optical communication links where digital signal processing (DSP) is removed to limit the complexity and power consumption. In these links, the filter can compensate electrical bandwidth limitations and distortion introduced by chromatic dispersion in the fiber. The complex filter is implemented by combining 4 distributed analog finite impulse response (FIR) filters to obtain the necessary response. The filter delays are implemented using active delay cell structures to create a compact solution. The analog filter is implemented in a 55nm BiCMOS technology and consumes 185 mW core power for 5 complex filter taps. Performance is evaluated using S-parameter measurements, noise and linearity measurements and real-time system experiments using 112 Gb/s 16-QAM modulated signals.

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“…At high speed, e.g. 20 Gb/s or beyond, it is difficult to design high precision delay line which is easily affected by the process, voltage, temperature (PVT) [6][7][8]. Similarly, the continuous time linear equalizer (CTLE) can also eliminate the pre-cursor and post-cursor by increasing the high-frequency components of the signal.…”

Section: Introductionmentioning

confidence: 99%

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

Zhang

Zhan

2017

Lecture Notes in Computer Science

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This paper presents a 20 Gb/s receive equalizer including an adaptive continuous time linear equalizer (CTLE) and a 2-tap half-rate decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE can adjust the ratio of high frequency and low frequency components adaptively by detecting the energy at both ends of a slicer and then generating a control signal by an integrator. Following the CTLE is a half-rate DFE which can get a better trade-off between the working speed and design complexity especially for the case of 20 Gb/s or above. The chip area including pads and chipguarding is about 0.72×0.86 mm 2 and the power consumption is about 528 mW. Post simulation results show that the horizontal eye opening of the equalized data can be up to 0.9 UI at 20 Gb/s.

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A 0.003 mm²5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE

Cited by 7 publications

References 5 publications

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

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A 0.003 mm25.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE

Cited by 7 publications

References 5 publications

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Analog I/Q FIR Filter in 55-nm SiGe BiCMOS for 16-QAM Optical Communications at 112 Gb/s

A 20 Gb/s Wireline Receiver with Adaptive CTLE and Half-Rate DFE in 0.13 µm Technology

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A 0.003 mm²5.2 mW/tap 20 GBd inductor-less 5-tap analog RX-FFE