A 0.0014 mm<sup>2</sup>, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits

Livanelioglu, Can; Choi, Woojun; Kim, Dong Hwan; Liao, Jiawei; Incandela, Rosario; Cristiano, Giorgio; Jang, Taekwang

doi:10.1109/vlsitechnologyandcir46769.2022.9830140

Cited by 2 publications

(1 citation statement)

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“…The amplifier chain (Fig. 3) consists of the capacitively-coupled LNA and VGA, whose DC feedback is implemented with segmented duty-cycled resistors (SDRs) for robustness and area efficiency [9]. The bandwidth of the amplifier chain can be adjusted by capacitor banks at the VGA.…”

Section: Proposed Neural Interface Systemmentioning

confidence: 99%

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

Choi

Chen

Kim

et al. 2023

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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This paper presents a neural interface that senses the electrical double layer (EDL) capacitance as a function of the ion concentration produced by neurons firing action potentials (AP). Unlike conventional microelectrode arrays (MEAs) detecting voltage, capacitance sensing allows access to multiple recording sites with a single wire using code-division multiplexing (CDM), thereby significantly reducing the number of required interconnects. In this work, we implemented 32 drivers and 32 analog front-end circuits (AFEs) to realize 1,024 channel concurrent neural recordings while using a total of 64 interconnects and improving area efficiency for large-scale integration. This work achieves 9.7μW power/ch and 0.005mm 2 area/ch efficiency with the highest electrode density of 10,000mm -2 , and the fewest interconnects to the authors' best knowledge.

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Section: Proposed Neural Interface Systemmentioning

confidence: 99%

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

Choi

Chen

Kim

et al. 2023

2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits)

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An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance

Atzeni,

Livanelioglu,

Arjmandpour

et al. 2024

IEEE J. Solid-State Circuits

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A 0.0014 mm², 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits

Cited by 2 publications

References 0 publications

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance

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A 0.0014 mm2, 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits

Cited by 2 publications

References 0 publications

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

A 1,024-Channel, 64-Interconnect, Capacitive Neural Interface Using a Cross-Coupled Microelectrode Array and 2-Dimensional Code-Division Multiplexing

An Impedance-Boosted Transformer-First Discrete-Time Analog Front-End Achieving 0.34 NEF and 389-MΩ Input Impedance

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Product

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A 0.0014 mm², 1.18 TΩ Segmented Duty-Cycled Resistor Replacing Pseudo-Resistor for Neural Recording Interface Circuits