A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS

Oh, Jaewon; Cho, Seonghwan

doi:10.1109/lssc.2024.3452280

IEEE Solid-State Circuits Lett.

2024

DOI: 10.1109/lssc.2024.3452280

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A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS

Jaewon Oh,

Seonghwan Cho

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A 0.001-mm², 1.15–11-GHz Background Quadrature Phase and Duty-Cycle Error Corrector Using a NAND- Based Phase Detector in 28-nm CMOS

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References 8 publications

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