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Bracale, A.; Ferlet-Cavrois, V.; Fel, N.; Pasquet, Daniel; Gautier, Jean-Luc; Pelloie, J.L.; Poncharra, J. du Port de

doi:10.1023/a:1008332732738

Cited by 83 publications

(3 citation statements)

References 14 publications

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“…2(a) in the frequency range from 10 MHz to 10 GHz, similar to [24]- [26]. The series resistances Rg, Rd and Rs are extracted beforehand with Bracale's method [27]. The resulting fitting of Ydd(f) and measurements at the ZTC bias point is shown in Figs.…”

Section: B Extraction Of Substrate and Back-gate Nodes Modelmentioning

confidence: 99%

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

Nyssens

Rack

Halder

et al. 2021

IEEE Electron Device Lett.

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This paper proposes an original approach to separately characterize self-heating and substrate effects in Fully-Depleted Silicon-on-Insulator (FD-SOI) devices. As both dynamic self-heating and drain to source coupling through the back-gate and substrate of an FD-SOI MOSFET induce a frequency transition in the Y-parameters in a common frequency range, it is crucial to properly separate them for further modeling. The proposed novel method is based on the extraction of the back-gate and substrate networks from the S-parameters measured at the zerotemperature coefficient bias. It enables the accurate and unambiguous extraction of thermal impedance for different biases, thus providing the extraction of the device thermal resistance and capacitance for different power levels from S-parameters measurements.

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Section: B Extraction Of Substrate and Back-gate Nodes Modelmentioning

confidence: 99%

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

Nyssens

Rack

Halder

et al. 2021

IEEE Electron Device Lett.

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“…1(b)) [10]. To this aim, the parasitic source/drain resistances (R S , R D ) which are extracted from HF measurements are based on the Bracale's approach at zero drain bias [9]. The results are doublechecked using the conventional DC resistance extraction method via y-intercept extrapolation of 1/g DS (=R S +R D ) as a function of 1/(V G -V TH ) at V DS =0, for example, as plotted in Fig.…”

Section: De-embedding Proceduresmentioning

confidence: 99%

HF Characterisation of sub-100nm UTB-FDSOI with TiN/HfO₂ Gate stack

Lim

Rozeau

Buj

et al. 2008

2008 9th International Conference on Ultimate Integration of Silicon

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For the first time, the High Frequency (HF) performance of an Ultra-Thinned Body (UTB) Fully Depleted Silicon-On-Insulator (FDSOI) incorporating TiN/HfO2 gate stack is reported. UTB-FDSOI with longer unit width W U (same total width W TOT ) features (results in) higher g m leading to better HF performance. Despite of the mobility degradation due to the quality of the interface between the high-K dielectric and silicon, the measured transition frequency (f T ) still correspond well to that predicted from the ITRS roadmap, and can also be considered as the first ever experimental f T measured fit for the Low STand-by Power (LSTP)-based RF/mobile application. IntroductionThe continuous advancement in scaling of the CMOS technology has allowed MOSFET to be an alternative and a more competitive candidate to the III-V technology in the millimetre wave range applications. Several new architectures and new materials have been introduced into MOSFET design to address the ever worsening Short Channel Effects (SCEs) when scaling below 100nm gate length, in particular the leakage current which has to be very low for the power-hungry and battery life-limited mobile/wireless-based applications. One of the effective solutions to improve SCEs is to use ultra-scaled UTB-FDSOI with undoped channel, which has been successfully demonstrated either experimentally [1,2] or via modelling/simulation [3]. It is known that when silicon channel in UTB-FDSOI is left undoped, this will result in threshold voltage (V TH ) to be completely controlled by the gate workfunction (preferably metal gate with workfunction near midgap) [3][4] and also the silicon thickness t SI (thinner t SI ensures better control of the channel) [3,5]. Furthermore, with the possibility of integration of the high-K dielectric material to substitute the thin gate silicon oxide, foundries have further proven the extra scaling capability of UTB-FDSOI to as small as 32nm node [6], without any severe penalties in SCEs. In this paper for the first time, HF characterisation of sub-100nm UTB-FDSOI featuring metal gate (TiN) and high-K gate dielectric (HfO 2 ) is reported. Using both DC and

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“…Onwafer open and short patterns were utilized to subtract padrelated capacitance and inductance components from measured scattering parameters (S-parameters). 19) Figure 3(a) plots a measured short-circuit current-gain (|h 21 | 2 ), a Mason's unilateral gain (U g ), and a maximum stable gain (MSG) after de-embedding pad-related parasitic components for the device with L g = 25 nm and W g = 2 × 20 μm at V DS = 0.5 V and V GS = 0.15 V near the peak g m bias condition. We As shown in Fig.…”

mentioning

confidence: 99%

L_g = 25 nm InGaAs/InAlAs high-electron mobility transistors with both f_T and f_max in excess of 700 GHz

Yun

Baek

et al. 2019

Appl. Phys. Express

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In this paper, we report an L g = 25 nm InGaAs/InAlAs HEMT on InP substrate that delivers excellent high-frequency characteristics. The device exhibited a value of maximum transconductance (g m_max) = 2.8 mS μm−1 at V DS = 0.8 V and on-resistance (R ON) = 279 Ω μm. At I D = 0.56 mA μm−1 and V DS = 0.5 V, the same device displayed an excellent combination of f T = 703 GHz and f max = 820 GHz. To the best of the authors’ knowledge, this is the first demonstration of a transistor with both f T and f max over 700 GHz on any material system.

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Cited by 83 publications

References 14 publications

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

HF Characterisation of sub-100nm UTB-FDSOI with TiN/HfO₂ Gate stack

L_g = 25 nm InGaAs/InAlAs high-electron mobility transistors with both f_T and f_max in excess of 700 GHz

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Untitled

Cited by 83 publications

References 14 publications

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

On the Separate Extraction of Self-Heating and Substrate Effects in FD-SOI MOSFET

HF Characterisation of sub-100nm UTB-FDSOI with TiN/HfO2 Gate stack

Lg = 25 nm InGaAs/InAlAs high-electron mobility transistors with both fT and fmax in excess of 700 GHz

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Product

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HF Characterisation of sub-100nm UTB-FDSOI with TiN/HfO₂ Gate stack

L_g = 25 nm InGaAs/InAlAs high-electron mobility transistors with both f_T and f_max in excess of 700 GHz