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Kästner, G.; Breitenstein, O.; Scholz, Roland; Reiche, M.

doi:10.1023/a:1020152215266

Cited by 9 publications

(5 citation statements)

References 16 publications

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“…9 Strong bonding of 150 mm GaAs wafers has also been reported previously. 10 The intimate mating of these similar wafers benefits from high ͑Ͼ800°C͒ or moderate ͑400-800°C͒ temperature anneal, which is prohibited in InP-to-Si wafer bonding due to large thermal mismatch and the requirement to maintain a desired doping profile. Warner et al have demonstrated the bonding of the largest available 150 mm InP wafer and SOI substrates via a low-temperature process recently.…”

mentioning

confidence: 99%

High-Quality 150 mm InP-to-Silicon Epitaxial Transfer for Silicon Photonic Integrated Circuits

Liang

Bowers

Oakley

et al. 2009

Electrochem. Solid-State Lett.

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We demonstrate the transfer of the largest ͑150 mm in diameter͒ available InP-based epitaxial structure to the silicon-on-insulator substrate through a direct wafer-bonding process. Over 95% bonding yield and a void-free bonding interface was obtained. A multiple quantum-well diode laser structure is well-preserved after bonding, as indicated by the high-resolution X-ray diffraction measurement and photoluminescence ͑PL͒ map. A bowing of 64.12 m is measured, resulting in a low bonding-induced strain of 17 MPa. PL measurement shows a standard deviation of 1.09% across the entire bonded area with less than 1.1 nm wavelength shift from the as-grown wafer.The integration of dissimilar materials is of great interest to enable silicon photonics and enable optical interconnects in future microprocessors. The wavelength transparency of Si in the telecom window ͑1.3-1.6 m͒ is another compelling reason to integrate microphotonics and microelectronics. A major challenge for this integration is the incompatibility of the III-V compound and Si semiconductors used to implement microphotonics and microelectronics, respectively. Si and InP have an 8.1% lattice mismatch, making heteroepitaxial growth of InGaAsP compounds on Si with low misfit dislocation density difficult. 1 A hybrid silicon evanescent platform ͑HSEP͒ developed recently is a promising approach to realize verylarge-scale photonic integrated circuits ͑PICs͒ on low-cost, complementary metal-oxide semiconductor ͑CMOS͒-compatible Si wafers. 2 Relying on a low-temperature direct wafer-bonding process, InP-based epitaxial structures have been transferred onto the prepatterned silicon-on-insulator ͑SOI͒ substrate reliably, which has enabled robust hybrid evanescent lasers, 3 amplifiers, 4 photodetectors, 5 and modulators 6 and the successful integration of them. 7 To date, all these components were fabricated in a 1 cm 2 chip scale. Wafer-scale processing has not yet been demonstrated.Wafer-scale bonding has been widely used to manufacture commercial SOI substrates 8 up to 300 mm in diameter. 9 Strong bonding of 150 mm GaAs wafers has also been reported previously. 10 The intimate mating of these similar wafers benefits from high ͑Ͼ800°C͒ or moderate ͑400-800°C͒ temperature anneal, which is prohibited in InP-to-Si wafer bonding due to large thermal mismatch and the requirement to maintain a desired doping profile. Warner et al. have demonstrated the bonding of the largest available 150 mm InP wafer and SOI substrates via a low-temperature process recently. 11 Chemical mechanical polishing ͑CMP͒ and ϳ200 nm plasma-enhanced chemical vapor deposition ͑PECVD͒ of SiO 2 at the bonding interface were employed to planarize the III-V surface and, more importantly, to absorb the gas by-products ͑H 2 O and H 2 ͒ from the intrinsic interface polymerization reactions, minimizing the formation of interfacial voids. Both CMP and thick interface dielectric, however, are impractical for maintaining global integrity of the III-V epitaxial structure and optical coupling between III-V and S...

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mentioning

confidence: 99%

High-Quality 150 mm InP-to-Silicon Epitaxial Transfer for Silicon Photonic Integrated Circuits

Liang

Bowers

Oakley

et al. 2009

Electrochem. Solid-State Lett.

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“…SiO 2 based wafer-scale bonding has been widely used to manufacture commercial SOI substrates (8) up to 300 mm in diameter (9). Strong bonding of 150 mm GaAs wafers has also been reported previously (10). The intimate mating of these similar wafers benefits from high (>800 °C) or moderate (400-800 °C) temperature anneal, which is prohibited in InP-to-Si wafer bonding due to large thermal mismatch and the requirement to maintain a desired doping profile.…”

Section: Introductionmentioning

confidence: 56%

150 mm InP-to-Silicon Direct Wafer Bonding for Silicon Photonic Integrated Circuits

Liang¹,

Fang²,

Oakley³

et al. 2008

ECS Trans.

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A low-temperature direct wafer bonding process was developed to realize the high-quality transfer of the largest (150 mm in diameter) available InP-based epitaxial structure onto the prepatterned silicon-on-insulator (SOI) substrate. Over 95% bonding yield and a void free bonding interface was obtained. A InGaAsP multiple quantum-well (MQW) diode laser structure is well preserved after bonding, as indicated by the high-resolution X-ray diffraction (XRD) rocking curve measurement. XRD omega scans of the bonded wafers over a 9×9 matrix revealed a small bowing of only 64.12 µm, showing that the III-V epitaxial surface is relatively flat with low-strain. The first InGaAsP-based MQW hybrid Si evanescent racetrack ring lasers have been realized, showing comparable performance as previously InAlGaAs ring lasers.

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“…While current research laboratory studies mainly focus on experiments using relatively small semiconductor wafers or diced pieces, there have been a number of reports of bonding of full 4-, 6-, and 8-inch wafers. [89][90][91][92] The wafer-bonding scheme may be easily extended to larger wafers.…”

Section: What Is Semiconductor Wafer Bonding?mentioning

confidence: 99%

Semiconductor Wafer Bonding for Solar Cell Applications: A Review

Tanabe

2023

Adv Energy and Sustain Res

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Wafer bonding is a highly effective technique for integrating dissimilar semiconductor materials while suppressing the generation of crystalline defects that commonly occur during heteroepitaxial growth. This method is successfully applied to produce efficient solar cells, making it an important area of research for photovoltaic devices. In this article, a comprehensive review of semiconductor wafer‐bonding technologies is provided, focusing on their applications in solar cells. Beginning with an explanation of the thermodynamics of wafer bonding relative to heteroepitaxy, the functionalities and advantages of semiconductor wafer bonding are discussed. An overview of the history and recent developments in high‐efficiency multijunction solar cells using wafer bonding is also provided. Bonded solar cells made of various semiconductor materials are reviewed and various types of wafer‐bonding methods, including direct bonding and interlayer‐mediated bonding, are described. Additionally, other technologies that utilize wafer bonding, such as flexible cells, thin‐film transfer, and wafer reuse techniques, are covered.

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Untitled

Cited by 9 publications

References 16 publications

High-Quality 150 mm InP-to-Silicon Epitaxial Transfer for Silicon Photonic Integrated Circuits

High-Quality 150 mm InP-to-Silicon Epitaxial Transfer for Silicon Photonic Integrated Circuits

150 mm InP-to-Silicon Direct Wafer Bonding for Silicon Photonic Integrated Circuits

Semiconductor Wafer Bonding for Solar Cell Applications: A Review

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