2018
DOI: 10.1016/j.mejo.2018.06.012
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84% High efficiency dynamic voltage scaler with nano-second settling time based on charge-pump and BWC-DAC

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Cited by 1 publication
(3 citation statements)
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“…Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance RL. It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15]. Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size.…”
Section: Experimental Environmentmentioning
confidence: 89%
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“…Figure 22 shows the post-layout simulation result of the voltage ripple along with a wide range load resistance RL. It changed exponentially from 90 µV to 8.43 mV, a significantly smaller ripple voltage than previous designs reported in [9,13,15]. Figure 21 shows the post-layout simulation result of the output voltage ripple for the above SSC-DVS test chip, which was obtained with a wide range of capacitor size.…”
Section: Experimental Environmentmentioning
confidence: 89%
“…We conducted measured results and post-layout simulations with an input voltage of 1.5 V to produce an output voltage range of 0.085-1.4 V, which demonstrated a power efficiency of 85% for a load current of 550 µA with a voltage ripple of as low as 2.656 mV for a 2 KΩ resistor load.Energies 2019, 12, 625 2 of 22 result in significant degradation in their energy efficiency. Moreover, to add more conversion ratios to switched-capacitor (SC) voltage converters, like a series-parallel SC converter, often increases the design complexity and the area of capacitor array while degrading the efficiency [8][9][10][11][12][13].Loai G. Salem et al [14] presented a voltage converter based on recursive switched-capacitor topology. It achieves 2 n conversion ratios with a peak efficiency of 85.8%.…”
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confidence: 99%
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