8-Bit Carry Look Ahead Adder Using MGDI Technique

Babu, P. Ashok; Nagaraju, V.; Vallabhuni, Rajeev Ratna

doi:10.1007/978-981-16-2919-8_22

Cited by 9 publications

(10 citation statements)

References 9 publications

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“…The adder presented in Ref. [12] has much less propagation delay compared to other adder models. The proposed adder was implemented on 90 nm technologies using track environment and its main purpose is to use the modified gate diffusion input (MGDI) technology to develop and implement a CLA.…”

Section: Literature Reviewmentioning

confidence: 99%

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Design and analysis of a novel fast adder using logical effort method

tavakolaee

Ardeshir

Baleghi

2023

IET Computers & Digital Tech

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Addition, as one of the fundamental math operations, is applied widely in Very‐large‐scale integration systems and digital signal processing, such that the computational speed of a system depends mainly on the computational speed of its adders. There are various types of digital adders based on different methods. A novel adder is proposed which performs addition based on a path with a fewer number of levels, and, hence, with higher computational speed and lower power consumption. The goal and innovation is to design a structured fast adder that has a block that can be expanded to higher bits, and in this design, the calculation speed and power consumption of the proposed circuit are optimal. Each proposed adder circuit has several levels, and the formulae of each level are stated. Each level of the circuit is designed with a number of multiplexers and OR gates. The performance of the proposed adder has been investigated and evaluated in two parts of mathematical calculations and simulation, and it has also been compared with other existing fast adders, such as ripple carry adder, carry skip adder, carry select adder, carry look ahead adder and prefix kogge‐stone in cases of 8, 16, 32 and 64 bits. The results show that the proposed collector has a good performance compared to other adders‐based power consumption, power delay product and delay area product metrics.

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Section: Literature Reviewmentioning

confidence: 99%

“…In Ref. [12], a CLA adder is proposed using the modified Gate diffusion technique, which reduces the delay in the adder. The adder presented in Ref.…”

Section: Background and Literature Reviewmentioning

confidence: 99%

Design and analysis of a novel fast adder using logical effort method

tavakolaee

Ardeshir

Baleghi

2023

IET Computers & Digital Tech

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“…[2] The combinational postponement is expanded due to the utilization of XOR & AND entryways. [29][30][31][32][33][34][35] By altering the ripple carry adder for improving region, CSLALOT is planned. [3] However, the speed of the engineering is decreased by the use of countless gatherings.…”

Section: Introductionmentioning

confidence: 99%

CSA Implementation Using Novel Methodology: RTL Development

2023

VLSI

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Carry Select Adder (CSLA) is an essentially utilized adder on account of its higher computational speed. CSLA is utilized in the space of incorporation frameworks. This paper proposes a CSLA design by carrying out the Logic Optimization Technique (ZFCLOT) using Zero Finding Logic contrasted with ordinary Zero Finding Logic (ZFC). This paper notices the different presentation measurements like area, power, delay, area delay product (ADP), power delay product (PDP) and effectiveness. Approval of the ZFCLOT put together CSLA is displayed with respect to Cadence stage utilizing 45 nm platform. The presented CSLA utilizing ZFCLOT has shown advanced execution measurements, explicitly, region and power improvement of 47.287% and 49.1%, separately contrasted with the current standard plans.

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“…These filters provide the linear model, inverse model of the unknown system and predict the present value of the random signal. [16][17][18][19][20][21][22][23][24][25] They can be designed as FIR or IIR filters. The adaptive FIR is more preferred because of its stability and easy updating of the filter coefficients.…”

Section: Introductionmentioning

confidence: 99%

Digital Filter based Adder Module Realization High-Speed Switching Functions

2023

VLSI

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FIR filter bank play a vital role in any signal processing systems. The FIR filter is used to implement any frequency response digitally. Usually, the FIR filters contain multipliers, adders and many delays. As we know, the number of MAC operations (multiply and accumulate) makes the FIR filter less efficient and increases hardware complexity. So in this project, we included DA (Distributed Arithmetic) architecture in designing the efficient adaptive FIR filter. The pipelined Distributive Arithmetic architecture provides less power, less area and high values of throughput in creating an adaptive FIR filter. These are used in Echo cancellations, Radio channel equalizers and speech coding. DA architecture also helps in improving the processing speed of the FIR filter by eliminating the number of multipliers. A reconfigurable filter design can be achieved with the help of this Distributive Arithmetic architecture. Here the sum of the partial products which is pipelined is passed as the input values, and it is stored in the LUT (lookup tables) of the distributive architecture. By replacing the adder of the shift accumulation unit with a carry-save adder, the area of the proposed design is reduced. By placing the ripple carry adder, the size and delay are reduced to a further extent. Here we will use the Xilinx ISE tool to verify the simulation result, area required and time consumed.

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8-Bit Carry Look Ahead Adder Using MGDI Technique

Cited by 9 publications

References 9 publications

Design and analysis of a novel fast adder using logical effort method

Design and analysis of a novel fast adder using logical effort method

CSA Implementation Using Novel Methodology: RTL Development

Digital Filter based Adder Module Realization High-Speed Switching Functions

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