8.7 A 4-to-10.5Gb/s 2.2mW/Gb/s continuous-rate digital CDR with automatic frequency acquisition in 65nm CMOS

Abstract

Continuous-rate clock-and-data recovery (CDR) circuits with automatic frequency acquisition offer flexibility in both optical and electrical communication networks, and minimize cost with a single-chip multi-standard solution. The two major challenges in the design of such a CDR are: (a) extracting the bit-rate from the incoming random data stream, and (b) designing a wide-tuning-range low-noise oscillator. Among all available frequency detectors (FDs), the stochastic divider-based approach has the widest frequency acquisition range and is well suited for sub-rate CDRs [1]. However, its accuracy strongly depends on input transition density (0 ≤ ρ ≤ 1), with any deviation of ρ from 0.5 (50% transition density) causing 2×(ρ-0.5)×10 6 ppm of frequency error. In this paper, we present an automatic frequency-acquisition scheme that has unlimited range and is immune to variations in transition density. Implemented using a conventional bang-bang phase detector (BBPD), it requires minimum additional hardware and is applicable to sub-rate CDRs as well. Instead of using multiple LC oscillators that are carefully designed to cover a wide frequency range [2,3], a ring-oscillator-based fractional-N PLL is used as a digitally controlled oscillator (DCO) to achieve both wide range and low noise, and to decouple the tradeoff between jitter transfer (JTRAN) bandwidth and ringoscillator-noise suppression. Figure 8.7.1 depicts the developed digital CDR architecture. It is composed of a frequency-locked loop (FLL), and a delay-and phase-locked loop (D/PLL). Both the FLL and D/PLL are updated using early/late (E/L) signals provided by the BBPD.In the FLL, frequency-detection logic block (FDL) operates on E/L signals and drives the DCO to within the pull-in range of the D/PLL through accumulator ACC F . Both loss-of-lock detection (LOLD) and lock detection (LD) needed to ensure seamless switching between data-rates are also implemented in the FDL. LOLD triggers a new frequency acquisition when the error (ΔF = F DCO -F DIN ) between DCO frequency and data rate exceeds 1000ppm. Lock is declared when ΔF is smaller than 500ppm.The D/PLL is composed of a digital DLL and a digital PLL, and can be viewed as the digital equivalent of the architecture reported in [2]. Similar to its analog counterpart, the digital D/PLL features a decoupled JTRAN bandwidth and jitter tolerance (JTOL) corner frequency, and exhibits well-controlled JTRAN bandwidth even in the presence of BBPD gain variations caused by input jitter [3]. Unlike [2], our D/PLL does not need large on-chip capacitors and the DCO is implemented using a fractional-N PLL employing a single ring oscillator instead of multiple LC oscillators. Additionally, to maximize JTOL, the digitally controlled delay line (DCDL) is biased at its mid-delay point in steady state by the path containing gain block K O and accumulator ACC O . The path containing divideby-H and accumulator ACC H is used to prevent false locking as discussed later.The principle behind the BBPD-based frequency detector (FD) i...

A 4-to-10.5 Gb/s Continuous-Rate Digital Clock and Data Recovery With Automatic Frequency Acquisition

“…7 [15]. It consists of three loops: 1) a frequency-locked loop (FLL); 2) a delay-locked loop (DLL); and 3) a PLL.…”

“…8 [15]. Input data DIN is buffered using a two-stage limiting amplifier before feeding it to the DCDL.…”

An 8.2 Gb/s-to-10.3 Gb/s Full-Rate Linear Referenceless CDR Without Frequency Detector in 0.18 μm CMOS

“…In [3]- [5], referenceless digital CDRs were realized with a wide frequency acquisition range, but the threshold selection of their frequency detectors (FDs) relies on the data pattern and density, which leads to a tradeoff between the acquisition time and the robustness of FD operation. State-machine-based FDs can also greatly increase the capture range, but the maximum data rate of this type of FDs is limited by the delay and setup time of digital components [6], [7].…”

An Adaptive-Bandwidth Referenceless CDR with Small-area Coarse and Fine Frequency Detectors

“…The referenceless CDR satisfies this requirement. The referenceless CDR [3][4][5][6][7][8][9][10][11][12][13][14][15][16] extracts the clock signal from the received data signal alone without using any reference clock sources ( Fig. 1(b)).…”

“…This method is limited to a specific encoding scheme, such as the 2 7 -1 PRBS data for [8] and the 8B10B-encoded data for [9]. The third solution recovers the clock signal by using the randomness of input data [10][11][12][13]. The input data stream is divided by more than 1000 and the resultant output is applied to a frequency multiplier to recover the clock signal.…”