8.6fJ/step VCO-Based CT 2<sup>nd</sup>-Order $\Delta\Sigma$ ADC

Jayaraj, Akshay; Das, Abhijit; Arcot, Srinivas; Sanyal, Arindam

doi:10.1109/a-sscc47793.2019.9056932

Cited by 6 publications

(4 citation statements)

References 7 publications

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“…An interesting alternative is to operate the VCO in the inherently linear two-point frequency modulation scheme. This enables cascading switched-current VCO-based integrators [23]- [26] within digitally intensive high-order noise-shaping architectures, at the cost of an increased system complexity.…”

Section: A Compatibility Of Prior Art With Ulv Operationmentioning

confidence: 99%

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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This article demonstrates the potential of deepsubthreshold mixed-signal circuits in delivering medium-to-high performance to supply-constrained, energy-harvesting Internet of Things (IoT) sensing applications. This effort encapsulates the design and implementation of an ultra-low-voltage (ULV) 0.2-V open-loop VCO-based analog-to-digital converter (ADC). A replica VCO facilitates variation-aware VCO analog linearization. Analog phase-domain signal processing (APSP) techniques for beat-frequency extraction, phase-interpolation, and phase-folding relax constraints on both voltage-to-frequency analog circuitry and frequency-to-digital synchronous digital hardware. High-speed multi-phase frequency-to-digital converters (FDCs) and multi-rate digital back-end enable a sampling speed of 35 MS/s. The ADC prototype is implemented in 28-nm CMOS and achieves a peak SNDR of 64.4/59.9 dB, equivalent to an ENOB of 10.4/9.7 over 80-/160-kHz bandwidth (BW). The ADC core occupies an active area of 0.12 mm 2 and consumes 15.9 µW, resulting in a Walden and Schreier FoM of, respectively, 73.3/61.5 fJ/c-s and 161.4/159.9 dB at the corresponding BW configurations. Measurements across multiple ICs and supply voltages consolidate the value of variation-aware deep-subthreshold open-loop ADCs.

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Section: A Compatibility Of Prior Art With Ulv Operationmentioning

confidence: 99%

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

Nguyên

Schembari

Staszewski

2022

IEEE J. Solid-State Circuits

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“…The ADC achieves an FOM in the range of 79-102 fJ/conv-step for different input frequencies. Note that [35] achieves much lower FOM by using 2 nd order noise shaping loop; however, this benefit comes mostly due to reduced quantization noise and is orthogonal to the improvements in oscillator structure we report. Also, this improvement comes with a > 10X area penalty which may not be suited for neuron designs.…”

Section: Measurement Resultsmentioning

confidence: 57%

A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing

Zhang

Acharya

Basu

2021

IEEE Trans. Circuits Syst. I

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This paper presents a low-area and low-power consumption CMOS differential current controlled oscillator (CCO) for neuromorphic applications. The oscillation frequency is improved over the conventional one by reducing the number of MOS transistors thus lowering the load capacitor in each stage. The analysis shows that for the same power consumption, the oscillation frequency can be increased about 11% compared with the conventional one without degrading the phase noise. Alternatively, the power consumption can be reduced 15% at the same frequency. The prototype structures are fabricated in a standard 65 nm CMOS technology and measurements demonstrate that the proposed CCO operates from 0.7 − 1.2 V supply with maximum frequencies of 80 MHz and energy/cycle ranging from 0.11 − 0.38 pJ over the tuning range. Further, system level simulations show that the nonlinearity in currentfrequency conversion by the CCO does not affect its use as a neuron in a Deep Neural Network if accounted for during training.

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“…1. The ADC architecture is based on the work reported in [6]. The TRNG derives its entropy from thermal noise and jitter in the ADC and LSB of the ADC differential outputs are XOR-ed to produce TRNG bitstream as shown in Fig.…”

Section: Proposed Architecturementioning

confidence: 99%

33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator

Chandrasekaran

Jayaraj

Ramesh

et al. 2021

2021 IEEE International Symposium on Circuits and Systems (ISCAS)

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This work presents a true random number generator (TRNG) that uses noise and jitter in a continuous-time, deltasigma modulator (CTDSM) as entropy source. A multi-bit nonreturn-to-zero (NRZ) feedback digital-to-analog converter (DAC) ensures that input swing seen by the front-end integrators is small and dominated by CTDSM noise and jitter, thus allowing the proposed circuit to simultaneously operate as both CTDSM and TRNG which is a key differentiation of this work compared to state-of-the-art TRNGs. Voltage controlled ring oscillators are used to implement integrators in the proposed CTDSM. Fabricated in 65nm CMOS, the TRNG has an energy efficiency of 3pJ/bit at throughput of 33Mbps and 3.5pJ/bit at 200Mbps, and passes all NIST tests with a minimum pass rate> 0.96. The measured minimum entropy of the TRNG bits is > 0.9995 across multiple chips and voltage/temperature corners without any calibration.

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8.6fJ/step VCO-Based CT 2^nd-Order $\Delta\Sigma$ ADC

Cited by 6 publications

References 7 publications

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing

33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator

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8.6fJ/step VCO-Based CT 2nd-Order $\Delta\Sigma$ ADC

Cited by 6 publications

References 7 publications

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A Deep-Subthreshold Variation-Aware 0.2-V Open-Loop VCO-Based ADC

A 0.11–0.38 pJ/cycle Differential Ring Oscillator in 65 nm CMOS for Robust Neurocomputing

33-200Mbps, 3pJ/Bit True Random Number Generator Based on CT Delta-Sigma Modulator

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Product

Resources

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8.6fJ/step VCO-Based CT 2^nd-Order $\Delta\Sigma$ ADC