8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

Kim, Stephen T.; Shih, Yu-Jen; Mazumdar, Kaushik; Jain, Rachna; Ryan, Joseph F.; Tokunaga, Carlos; Augustine, Charles; Kulkarni, Jaydeep P.; Ravichandran, Krishnan; Tschanz, James; Khellah, Muhammad; De, Vivek

doi:10.1109/isscc.2015.7062972

Cited by 25 publications

(9 citation statements)

References 3 publications

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“…Table 1 compares the performance of the LAVS to the stateof-the-art. With a fully-integrated power tree option, the power density of our LAVS is two orders of magnitude higher than the best-in-class fully-integrated DC-DC converters in CMOS technologies without high-density capacitance options [1][2][3]. Compared to [4], we control the slew-rate i.e.…”

Section: Measurement Resultsmentioning

confidence: 99%

“…It is composed of a fully-integrated voltage selector which selects the core voltage VCORE between three shared voltage rails {VL,VM,VH} generated from an external DC-DC converter (out of the scope of this paper) in the range of 0.5-1V. Digital word SEL [1][2] selects the input voltage and a TR edge starts the voltage transitions (synchronized with external clock). The aim is to maintain a constant voltage slew rate (200ns/V) under any condition (voltage, activity factor, etc.)…”

Section: A Lavs System Overviewmentioning

confidence: 99%

“…One off-chip power supply per island is a costly solution to set the best energy point of each core. Therefore, to reduce the PCB surface area, BoM (Bill of Materials) and allow rapid VDD switching, fine grained DVS can be done using multiple on-die DC-DC converters (no external component needed) as suggested in [1][2][3] and shown in Figure 1. However, their lowpower densities (10's of mW/mm 2 in deep CMOS technology) compared to the digital power density (10's of W/mm 2 ) has negated the benefits of a fully-integrated power tree due to its costly silicon overhead.…”

Section: Introductionmentioning

confidence: 99%

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LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

Quelen

Marega

Bouquet

et al. 2018

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

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This paper presents a 95% power-efficient dutycycled LDO-assisted voltage selector (LAVS) for fine grained spatial and temporal voltage scaling in FDSOI 28nm technology. LAVS enables 200ns/V controlled transitions between three power rails over a 0.5-to-1V range while maintaining the digital activity of the supplied load. During transitions, current and voltage detections are proposed to protect power rails from reverse current. LAVS has a 13% Si area overhead to drive a 0.2mm 2 digital load. Thanks to a 100MHz-bandwidth LDO, which is only enabled during transition to save power consumption, the voltage selector also maintains a smooth voltage transition even if a digital load suddenly changes its activity factor (4mV/mA load transient). LAVS achieves 30pJ energy dissipation per voltage transition which is negligible compared to the power consumed by the digital load (50mW@0.2mm 2). This therefore allows a MHz dynamic voltage scaling rate.

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Section: Measurement Resultsmentioning

confidence: 99%

Section: A Lavs System Overviewmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

Quelen

Marega

Bouquet

et al. 2018

ESSCIRC 2018 - IEEE 44th European Solid State Circuits Conference (ESSCIRC)

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“…References [7] and [8] place fully integrated VRs along the periphery of the load block also requiring custom design to match the load dimensions. Such placement can also result in routing blockage due to heavy feed-through and other signal routing encountered across the block peripheries in SoC methodology.…”

Section: Motivation For Conductance Modulationmentioning

confidence: 99%

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

Jain

Kim

Vaidya

et al. 2015

IEEE J. Solid-State Circuits

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Switch conductance modulation techniques are demonstrated in a fully integrated multi-ratio switched-capacitor voltage regulator with hysteretic control, in 22 nm tri-gate CMOS with high-density MIM capacitor. We present (i) an adaptive switch-size scaling scheme for maximum efficiency tracking across a wide range of voltages and currents, governed by a frequency-based control law that is experimentally validated across multiple dies and temperatures and, (ii) a simple active ripple mitigation technique that modulates the gate drive of select MOSFET switches effectively in all conversion modes. Efficiency improvements up to 15% are measured under low output voltage and load conditions. Load-independent output ripple of 50 mV is achieved, enabling reduced interleaving. Test chip implementations and measurements demonstrate ease of integration in SoC designs, power efficiency benefits and EMI/RFI improvements.

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“…With the wide use of fine-grain power management in modern VLSI circuits [1,2], digital low dropout (LDO) voltage regulators are gaining significant research interests and a large number of digital LDO circuits are recently reported [3][4][5][6][7][8][9][10][11][12][13][14][15][16][17]. The transition from analog to digital LDOs is mainly due to the difficulties in designing power-efficient high-gain amplifiers at low-voltage and advanced technology nodes.…”

Section: Introductionmentioning

confidence: 99%

Digital LDO modelling techniques for performance estimation at early design stage

Leitner

Wang

2018

IET Circuits, Devices & Systems

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This work studies the transient responses and steady-state ripples of digital low dropout (LDO) voltage regulators. Simulation models as well as closed-form expressions are provided for estimating the LDO output settling behaviour after load current or reference voltage changes. Estimation equations for the magnitude and frequency of LDO output steady-state ripples are also presented. The accuracy of the developed models is verified by comparing estimation data with results obtained from circuit simulations. The use of the developed estimation equations in design space exploration is also demonstrated.

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8.6 Enabling wide autonomous DVFS in a 22nm graphics execution core using a digitally controlled hybrid LDO/switched-capacitor VR with fast droop mitigation

Cited by 25 publications

References 3 publications

LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

LDO-Assisted Voltage Selector Over 0.5-to-1V VDD Range for Fine Grained DVS in FDSOI 28nm with 200ns/V Controlled Transition

Conductance Modulation Techniques in Switched-Capacitor DC-DC Converter for Maximum-Efficiency Tracking and Ripple Mitigation in 22 nm Tri-Gate CMOS

Digital LDO modelling techniques for performance estimation at early design stage

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