8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2

LaCroix, Marc-Andre; Chong, Euhan; Shen, Weixiao; Nir, Ehud; Musa, F. A. S.; Mei, Haitao; Mohsenpour, Mohammad-Mahdi; Lebedev, S. F.; Zamanlooy, Babak; Carvalho, Carlos Vaz de; Xiao, Qian; Petrov, Dmitry; Wong, Henry; Ho, H. L.; Xu, Yang; Shahi, Sina Naderi; Krotnev, Peter; Feist, Christopher; Huang, Howard; Tonietto, Davide

doi:10.1109/isscc42613.2021.9366030

Cited by 35 publications

(15 citation statements)

References 4 publications

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“…At the input, bits are mapped to complex-valued symbols X [1] to X[N −1]. Each is selected from a pre-defined constellation, encoding log 2 (N S ) bits, where N S is the constellation size.…”

Section: A Discrete Multi-tonementioning

confidence: 99%

“…A Cyclic Prefix (CP), which is discussed later, is appended, and the signal u(t) is sent through the channel. At the receiver, the CP is removed from v(t), and the tones y [n] are sent through an FFT to recover symbols Y [1] to Y[N − 1]. Finally, they are decoded and converted back to bits.…”

Section: A Discrete Multi-tonementioning

confidence: 99%

“…At higher data rates, ISI is more detrimental, requiring more sophisticated filters. Moreover, the optimization of equalizer coefficients is a non-trivial problem, often requiring an LMS or even a genetic search algorithm [1], [18]. These controllers are also becoming more complex, worsening the problem.…”

Section: B Equalizationmentioning

confidence: 99%

“…T HE WIRELINE industry is approaching a turning point. Today's state-of-the-art 100Gb/s long-reach 4-PAM systems require complex equalization schemes to combat severe Inter-Symbol Interference (ISI) including feed-forward equalizers of 25+ taps [1], [2]. With an ever-increasing data-rate, transceiver complexity continues to worsen; it will soon lead to impractical power consumption [3].…”

Section: Introductionmentioning

confidence: 99%

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Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

IEEE Open J. Circuits Syst.

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This paper proposes a discrete multi-tone timing-recovery system with adaptive equalization for ultra-high-speed wireline applications. It combines frequency-domain clock recovery with decisiondirected equalization to improve receiver performance while eliminating the need for pilot carriers, thereby increasing spectral efficiency. Compared to a conventional pilot-carrier-based technique employing four pilot carriers and a 32-point FFT, this approach improves phase-error sensitivity by 3.6 times, tracking bandwidth by 1.7 times, increases the jitter tolerance slope by 20dB per decade at low frequency, and removes residual equalization error, resulting in an overall data-rate increase of 27%. The concept is validated at the system-level and gate-level through synthesis in an FPGA. A convergence analysis of both the adaptive equalizer and clock synchronization shows the system's ability to mitigate error propagation and remain synchronized in the presence of impairments. Finally, we highlight the system's ability to trade-off clock convergence versus phase error sensitivity. Either parameter can be adjusted by 15 times, optimizing the receiver over a broad range of signal conditions.INDEX TERMS Adaptive equalization, clock and data recovery (CDR), decision-directed equalization, discrete multi-tone (DMT), orthogonal frequency division multiplexing (OFDM), SERDES, single-tap equalization, timing recovery, wireline. JEREMY COSSON-MARTIN (Graduate Student Member, IEEE) received the B.A.Sc. degree in electrical engineering from Queen's University, Kingston, ON, Canada, in the spring of 2018. In the fall of 2018, he began an M.A.Sc. program at the University of Toronto, ON, Canada, under the supervision of Prof. A. Sheikholeslami. In 2019, he transferred into a Ph.D. program.In the summer of 2018, he joined Huawei Canada, Toronto, ON, Canada, as an intern, where he was involved in creating in-lab measurement scripts for a prototype 56-Gb/s SerDes integrated chip. He also received experience in 7-nm FinFET layout. Currently, he is researching multi-tone schemes for ultra-high-speed wireline applications.

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Section: A Discrete Multi-tonementioning

confidence: 99%

Section: A Discrete Multi-tonementioning

confidence: 99%

Section: B Equalizationmentioning

confidence: 99%

Section: Introductionmentioning

confidence: 99%

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Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Cosson-Martin

Shakiba

Sheikholeslami

2021

IEEE Open J. Circuits Syst.

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“…Then the signal processing is implemented by digital circuit, including the slicers, the DFE and so on. Thus, these receivers are widely used because of their design flexibility [3,4,5,6,7,8,9,10,11,12]. However, the design process limits the speed of receivers.…”

Section: Introductionmentioning

confidence: 99%

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

Han

Wang

2021

IEICE Electron. Express

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This paper presents a 56-Gbps four-level pulse amplitude modulation (PAM4) quarter-rate receiver based on amplitude rectification. Compared with the conventional three-comparator structure, the PAM4 signal is converted into a 2-digit gray-code rather than a 3-digit thermometer-code. The amplitude is detected to decode the least significant bit (LSB), which allows the proposed receiver to use significantly less power by reducing the number of comparators. An inverter-based common-mode voltage stabilization circuit (CVSC) is proposed to reduce the effect of common-mode level changes as the amplitude is determined. To minimize the feedback delay, the 2-digit gray-code is fed back to DFE's summer directly. By reducing the digit of the feedback signal, the power will be further reduced as the DFE tap increases. The device consumes 83.5 mW over a 55-nm process.

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A 135 GHz Direct-Digital 16-QAM Wireless and DWG Link

D’heer,

Reynaert

2024

Analog Circuits and Signal Processing

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8.4 A 116Gb/s DSP-Based Wireline Transceiver in 7nm CMOS Achieving 6pJ/b at 45dB Loss in PAM-4/Duo-PAM-4 and 52dB in PAM-2

Cited by 35 publications

References 4 publications

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

Timing Recovery and Adaptive Equalization for Discrete Multi-Tone Signalling in Wireline Applications

A 56-Gbps PAM4 amplitude-rectification-based receiver with threshold adaptation and 1-tap DFE

A 135 GHz Direct-Digital 16-QAM Wireless and DWG Link

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