7-bit 0.8&amp;#x2013;1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Yoshioka, Kentaro; Saito, Ryo; Danjo, Takumi; Tsukamoto, Sanroku; Ishikuro, Hiroki

doi:10.1109/vlsic.2014.6858374

Cited by 6 publications

(3 citation statements)

References 1 publication

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“…The calibrated SFDR is limited by HD2 which is likely the by‐product of the pseudo‐differential TWG and comparator. Table 1 compares the proposed ADC with state‐of‐the‐art ADCs

false(1 GS / s < f_{normals} < 6 GS / s)

[8–10]. The proposed ADC is better than similar specification flash ADCs and is comparable to subrange and SAR ADCs.…”

Section: Measurement Resultsmentioning

confidence: 99%

Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation

Saha¹,

Harjani²

2018

Electron. lett.

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A 2 × time-interleaved 1 GS/s 7b ADC is presented, which uses pulsewidth modulation and time domain quantisation for digitisation and is designed for wide channel bandwidths available at mm-wave frequencies. The area, resolution and power performance of the highly digital time-domain architecture is likely to scale with technology. The prototype ADC achieves 5.24 ENOB at a Nyquist rate while consuming 5.22 mW of power, resulting in a FOM Walden,nyq = 138.13 fJ/ conversion step in TSMC's 65 nm GP CMOS process.

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“…The calibrated SFDR is limited by HD2 which is likely the by‐product of the pseudo‐differential TWG and comparator. Table 1 compares the proposed ADC with state‐of‐the‐art ADCs

false(1 GS / s < f_{normals} < 6 GS / s)

[8–10]. The proposed ADC is better than similar specification flash ADCs and is comparable to subrange and SAR ADCs.…”

Section: Measurement Resultsmentioning

confidence: 99%

Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation

Saha¹,

Harjani²

2018

Electron. lett.

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“…The reconfigurable ADC [60][61][62][63][64] are in research using pipelined and SAR ADCs to configure the resolution and sampling rate depending upon the requirements. SAR ADC [68][69][70][71][72] is an analog circuit whose performance gets better with CMOS scaling process [73][74][75] and always employed for high speed, low power and high-resolution ADCs. The publication history of SAR ADC is noticeable from last two decades studying its performance enhancement [76][77].…”

Section: Fig 6: Zoomed In View Of Adc Core [21]mentioning

confidence: 99%

Analog to Digital Converters (ADC): A Literature Review

Dalmia

Sinha

2020

E3S Web Conf.

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The signal processing is advancing day by day as its needs and in wireline/wireless communication technology from 2G to 4G cellular communication technology with CMOS scaling process. In this context the high-performance ADCs, analog to digital converters have snatched the attention in the field of digital signal processing. The primary emphasis is on low power approaches to circuits, algorithms and architectures that apply to wireless systems. Different techniques are used for reducing power consumption by using low power supply, reduced threshold voltage, scaling of transistors, etc. In this paper, we have discussed the different types and different techniques used for analog to digital conversion of signals considering several parameters.

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“…In this paper, we propose Dynamic Architecture and Frequency Scaling (DAFS) to realize superlinear power scaling at high speed [3]. Using this technique, the ADC architecture is reconfigured between a binary search and flash ADC every conversion cycle, and the operating architecture is decided by examining the ADC conversion delay.…”

Section: Introductionmentioning

confidence: 99%

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC

Yoshioka

Saito

Danjo

et al. 2015

IEEE J. Solid-State Circuits

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Dynamic Architecture and Frequency Scaling (DAFS) is shown to realize superlinear power scaling in high-speed analog-to-digital converters (ADCs). To achieve both high-speed operation and low power consumption, the ADC architecture is reconfigured between binary search and flash every clock cycle, relying on the conversion delay. The proposed binary search/flash architecture reconfigurable ADC can be implemented with only a small modification to conventional binary search ADCs. By live configuring, the flash operation is adaptively performed when an excess delay is detected. DAFS not only significantly improves the power scaling but also compensates for transistor speed shifts due to process, voltage and temperature (PVT) variations. Therefore, DAFS can be used to improve the design margin of high-speed ADCs. A prototype subranging ADC fabricated in 65 nm CMOS technology operates up to 1220 MS/s and achieves an SNDR of 36.2 dB with a Nyquist input frequency. DAFS is active between 820-1220 MS/s and achieves peak power reduction of 30%, when compared with the power scaling when DAFS is disabled. A peak FoM of 85 fJ/conv. was obtained at 820 MS/s, which is nearly a twofold improvement over that of previously reported subranging ADCs.Index Terms-Binary search ADC, dynamic architecture and frequency scaling (DAFS), flash ADC, high-speed, power scaling, subranging ADC.

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7-bit 0.8–1.2GS/s Dynamic Architecture and Frequency Scaling subrange ADC with binary-search/flash Live Configuring Technique

Cited by 6 publications

References 1 publication

Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation

Highly digital 1 GS/s 7‐bit PWM ADC in 65 nm CMOS using time‐domain quantisation

Analog to Digital Converters (ADC): A Literature Review

Dynamic Architecture and Frequency Scaling in 0.8–1.2 GS/s 7 b Subranging ADC

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