7.6 A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

Hsieh, Sung-En; Wei, Chun-Hao; Xue, Cheng-Xin; Lin, Hung-Wei; Tu, Wei-Hsuan; Chang, En-Jui; Yang, Kai-Taing; Chen, Po-Heng; Liao, Wei-Nan; Low, Li Lian; Lee, Chia-Da; Lu, Allen-Cl; Jia, Liang; Cheng, Chih-Chung; Kang, Tzung-Hung

doi:10.1109/isscc42615.2023.10067335

Cited by 15 publications

(2 citation statements)

References 3 publications

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“…Therefore, 8-bit resolution is enough and proper for general purpose AI processors and is considered feasible even if analog technology is used for the MAC circuit. Charge domain mixed signal MACs have been implemented in AI processors [2][3][4][5][6][7][8][9][10].…”

Section: Introductionmentioning

confidence: 99%

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Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

Matsuzawa,

Martinez Alonso,

Miyahara

2023

Electronics

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This article describes the design and performance analysis of a charge domain mixed-signal multiply-accumulator (MAC) using RDAC, CDAC, and SAR-ADC with an 8-bit resolution for input, weight, and output. The arithmetic accuracy is mainly determined by the ADC, and the gain error has a significant impact. The mismatches and thermal noises of the RDAC and the CDAC are averaged by the number of multiply-accumulate units m connected to one ADC. As a result, if m is large enough, mismatches and thermal noises have a limited impact on the computation accuracy. Most of the computational energy is determined by the energy consumed by the SAR-ADC, and the computational energy per operation can be reduced by increasing m. This last metric is mainly determined by the charge and discharge energy of the CDAC for sufficiently large m values. Furthermore, since RDAC consumes energy unnecessarily, the turn-off timing of RDAC should be optimized. These MAC units have been designed and prototyped using 28 nm CMOS technology, integrating 12,288 arithmetic units while operating at 180 MHz, resulting in an arithmetic speed of 4.4 TOPS. The r-MVM accuracy is about 1% and a high energy efficiency of 240 TOPS/W as a MAC macro and 64.4 TOPS/W as a system has been achieved.

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Section: Introductionmentioning

confidence: 99%

“…Cont.Note:1 : Normalized to 8b input, 2 : Including I/O and test mode,3 : Including I/O, test mode, digital Ctrl., CLK Gen 4. : Peak performance with σ ≈ 1% at r-MVM test,5 : Calculated from area efficiency 6. : Active area of MS-MAC macro 7.…”

mentioning

confidence: 99%

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

Matsuzawa,

Martinez Alonso,

Miyahara

2023

Electronics

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From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits

Zhang,

Chen,

Chen

et al. 2023

Sci. China Inf. Sci.

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A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

Diaz-Madrid,

Domenech-Asensi,

Ruiz-Merino

et al. 2024

J Real-Time Image Proc

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In-memory computing (IMC) represents a promising approach to reducing latency and enhancing the energy efficiency of operations required for calculating convolution products of images. This study proposes a fully differential current-mode architecture for computing image convolutions across all four quadrants, intended for deep learning applications within CMOS imagers utilizing IMC near the CMOS sensor. This architecture processes analog signals provided by a CMOS sensor without the need for analog-to-digital conversion. Furthermore, it eliminates the necessity for data transfer between memory and analog operators as convolutions are computed within modified SRAM memory. The paper suggests modifying the structure of a CMOS SRAM cell by incorporating transistors capable of performing multiplications between binary (−1 or +1) weights and analog signals. Modified SRAM cells can be interconnected to sum the multiplication results obtained from individual cells. This approach facilitates connecting current inputs to different SRAM cells, offering highly scalable and parallelized calculations. For this study, a configurable module comprising nine modified SRAM cells with peripheral circuitry has been designed to calculate the convolution product on each pixel of an image using a $$3 \times 3$$ 3 × 3 mask with binary values (−1 or 1). Subsequently, an IMC module has been designed to perform 16 convolution operations in parallel, with input currents shared among the 16 modules. This configuration enables the computation of 16 convolutions simultaneously, processing a column per cycle. A digital control circuit manages both the readout or memorization of digital weights, as well as the multiply and add operations in real-time. The architecture underwent testing by performing convolutions between binary masks of 3 × 3 values and images of 32 × 32 pixels to assess accuracy and scalability when two IMC modules are vertically integrated. Convolution weights are stored locally as 1-bit digital values. The circuit was synthesized in 180 nm CMOS technology, and simulation results indicate its capability to perform a complete convolution in 3.2 ms, achieving an efficiency of 11,522 1-b TOPS/W (1-b tera-operations per second per watt) with a similarity to ideal processing of 96%.

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7.6 A 70.85-86.27TOPS/W PVT-Insensitive 8b Word-Wise ACIM with Post-Processing Relaxation

Cited by 15 publications

References 3 publications

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

Design and Performance Analysis of a [8/8/8] Charge Domain Mixed-Signal Multiply-Accumulator

From macro to microarchitecture: reviews and trends of SRAM-based compute-in-memory circuits

A real-time and energy-efficient SRAM with mixed-signal in-memory computing near CMOS sensors

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