7.5 A 3.3ns-access-time 71.2&amp;#x03BC;W/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Noguchi, Hiroki; Ikegami, Kazutaka; Kushida, K.; Abe, Keiko; Itai, Shogo; Takaya, Satoshi; Shimomura, N.; Ito, Junichi; Kawasumi, A.; Hara, Hiroyuki; Fujita, Shinobu

doi:10.1109/isscc.2015.7062963

Cited by 58 publications

(49 citation statements)

References 3 publications

Supporting

Mentioning

Contrasting

Order By: Relevance

“…2) By replacing volatile working memories such as static random access memories (SRAMs) and dynamic random access memories (DRAMs) by nonvolatile spintronics-based ones, i.e., magnetoresistive random access memories (MRAMs), one can drastically reduce the power consumption of ICs while maintaining high performance as was demonstrated in recent studies. [3][4][5][6][7][8] Spintronics memory devices can be classified into two categories according to their structure: two-and three-terminal devices. Both devices generally include a magnetic tunnel junction (MTJ), and the read operation is performed using the tunnel magnetoresistance (TMR) effect.…”

Section: Introductionmentioning

confidence: 99%

Magnetization switching schemes for nanoscale three-terminal spintronics devices

Fukami

Ohno

2017

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

Utilizing spintronics-based nonvolatile memories in integrated circuits offers a promising approach to realize ultralow-power and high-performance electronics. While two-terminal devices with spin-transfer torque switching have been extensively developed nowadays, there has been a growing interest in devices with a three-terminal structure. Of primary importance for applications is the efficient manipulation of magnetization, corresponding to information writing, in nanoscale devices. Here we review the studies of current-induced domain wall motion and spin-orbit torque-induced switching, which can be applied to the write operation of nanoscale three-terminal spintronics devices. For domain wall motion, the size dependence of device properties down to less than 20 nm will be shown and the underlying mechanism behind the results will be discussed. For spin-orbit torque-induced switching, factors governing the threshold current density and strategies to reduce it will be discussed. A proof-ofconcept demonstration of artificial intelligence using an analog spin-orbit torque device will also be reviewed.

show abstract

Section: Introductionmentioning

confidence: 99%

Magnetization switching schemes for nanoscale three-terminal spintronics devices

Fukami

Ohno

2017

Jpn. J. Appl. Phys.

View full text Add to dashboard Cite

show abstract

“…The silent stores optimization can be used with all NVMs. But since STT-RAM are quite mature as test chips already exist [4], [5] and show reasonable performance at device level compared to SRAM, we consider STT-RAM in this work.…”

Section: Introductionmentioning

confidence: 99%

How could compile-time program analysis help leveraging emerging NVM features?

Bouziane¹,

Rohou²,

Gamatié³

2017

2017 First International Conference on Embedded &Amp; Distributed Systems (EDiS)

View full text Add to dashboard Cite

Abstract-Beyond the fact of generating machine code, compilers play a critical role in delivering high performance, and more recently high energy efficiency. For decades, the memory technology of target systems has consisted in SRAM at cache level, and DRAM for main memory. Emerging non-volatile memories (NVMs) open up new opportunities, along with new design challenges. In particular, the asymmetric cost of read/write accesses calls for adjusting existing techniques in order to efficiently exploit NVMs. In addition, this technology makes it possible to design memories with cheaper accesses at the cost of lower data retention times. These features can be exploited at compile time to derive better data mappings according to the application and data retention characteristics. We review a number of compile-time analysis and optimization techniques, and how they could apply to systems in presence of NVMs. In particular, we consider the case of the reduction of the number of writes, and the analysis of variables lifetime for memory bank assignment of program variables.

show abstract

“…Although memory cells of STT-MRAM LLCs do not consume leakage power due to their non-volatility, their peripheral circuits are still suffering from the leakage problem [4]. Because STT-MRAM cells are twice or more denser than SRAM cells [5], the number of transistors for peripheral circuits of STT-MRAM LLC is larger than that of SRAM LLC even if the both LLCs occupy the same area.…”

Section: Introductionmentioning

confidence: 99%

“…Therefore, large sized and leaky transistors are required for peripheral circuits including write buffers, writebitline selectors and word line drivers. Thus, saving the leakage power of peripheral circuits is considered as one of the most critical problems of STT-MRAM LLCs in the industry [4].…”

Section: Introductionmentioning

confidence: 99%

See 1 more Smart Citation

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

Arima

Noguchi

Nakada

et al. 2015

2015 33rd IEEE International Conference on Computer Design (ICCD)

Self Cite

View full text Add to dashboard Cite

Implementing last level caches (LLCs) with STT-MRAM is a promising approach for designing energy efficient microprocessors due to high density and low leakage power of its memory cells. However, peripheral circuits of an STT-MRAM cache still suffer from leakage power because large and leaky transistors are required to drive large write current to STT-MRAM element. To overcome this problem, we propose a new power management scheme called Immediate Sleep (IS). IS immediately turns off a subarray of an STT-MRAM cache if the next access is predicted to be not critical in performance. Thus, IS can effectively reduce leakage energy with little impact on performance. Our experimental results show that our technique can save the leakage energy of an STT-MRAM LLC by 32% compared to an STT-MRAM LLC with the conventional scheme at the same performance.

show abstract

7.5 A 3.3ns-access-time 71.2μW/MHz 1Mb embedded STT-MRAM using physically eliminated read-disturb scheme and normally-off memory architecture

Cited by 58 publications

References 3 publications

Magnetization switching schemes for nanoscale three-terminal spintronics devices

Magnetization switching schemes for nanoscale three-terminal spintronics devices

How could compile-time program analysis help leveraging emerging NVM features?

Immediate sleep: Reducing energy impact of peripheral circuits in STT-MRAM caches

Contact Info

Product

Resources

About