67 dB SNDR 20 kHz BW SC third‐order  modulator with single Op‐Amp and 20 µW power consumption for bio‐medical applications

Sharma, Vivek; Kumar, Yogesh; Vasantha, M. H.

doi:10.1049/iet-cds.2019.0414

Cited by 3 publications

(1 citation statement)

References 28 publications

(18 reference statements)

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“…ΣΔ ADCs are oversampled converters, comprising of either a Switched-Capacitor (SC) or a Continuous-Time (CT) ΣΔ Modulator. A state-of-the-art SC implementation provides high precision and accuracy but due to switched integrators it suffers from stringent settling and slew requirements that lead to more power consumption [11,12]. Compared to SC, CT architecture consumes less power due to inherent anti-alias filtering that obviates the need for a dedicated analog filter required in the signal acquisition system.…”

Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Kavitha

Akhila²,

Kannan

2023

Eng. Technol. Appl. Sci. Res.

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The recent developments in biosignal acquisition devices for continuous supervision of cardiovascular signs of high-risk patients require a high-precision and low-power Analog Front End (AFE) circuit. The proposed design adopts Continuous-Time (CT) Sigma-Delta Modulator (ΣΔM) architecture to achieve high resolution and SIgnal-to-Noise And Distortion ratio (SINAD) requirements. The proposed modulator is a second-order CT-ΣΔM with Cascade of Integrators Feed-Forward (CIFF) architecture that consists of a CT loop filter, a single-bit quantizer, and a Digital-to-Analog Converter (DAC). The use of single-bit quantization in the design reduces circuit complexity and power consumption. To use the designed ΣΔM for measuring ECG signals, a bandwidth (Bw) of 150 Hz is considered with a sampling frequency (fs) of 153.6kHz to achieve an oversampling ratio of 512. The design is simulated in a standard Cadence Virtuoso EDA tool at 180nm CMOS technology, operating at 1.8V supply voltage at the block level. The simulation results for the designed modulator show that SINAD is 104.5dB, the Effective Number Of Bits (ENOB) is 17.06bits, with power consumption of 24µW, and achieves Schreier’s Figure-Of-Merit (FOM) equal to 172.45dB.

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Section: Introductionmentioning

confidence: 99%

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Kavitha

Akhila²,

Kannan

2023

Eng. Technol. Appl. Sci. Res.

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A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

Hemmati

Aghdam

2021

AEU - International Journal of Electronics and Communications

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A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

Wang,

et al. 2023

J CIRCUIT SYST COMP

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A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9[Formula: see text]dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256[Formula: see text]kHz and 312.5[Formula: see text]Hz input with a differential-mode voltage of 700[Formula: see text]mV sinusoidal waveform. Based on SMIC 180[Formula: see text]nm/1.8[Formula: see text]V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52[Formula: see text]dB SNDR, 18.90-bit ENOB, and 8.40[Formula: see text]mW power consumption, which correspond to FoM[Formula: see text] and FoM[Formula: see text] of 0.067[Formula: see text]pJ/step and 163.27[Formula: see text]dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.

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67 dB SNDR 20 kHz BW SC third‐order modulator with single Op‐Amp and 20 µW power consumption for bio‐medical applications

Cited by 3 publications

References 28 publications

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

Design and Implementation of a Second Order Continuous-Time ΣΔ Modulator for ECG Signal Acquisition

A low-power CT 2nd order Delta Sigma modulator using a new design methodology for biomedical applications

A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

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