6.8 A 1.5V 33Mpixel 3D-stacked CMOS image sensor with negative substrate bias

Data converters using continuous time sigma delta modulators with VCO-based integrator and quantizer for ultra low power applications

“…FoM of 125fJ/conv-step for different input frequencies, which is the lower or at par with other ultra-low voltage sigma delta modulators [14,15,20,21]. The calibration algorithm takes less than 2 13 cycles, which is the fastest among similar works.…”

“…During the calibration cycle, the non-linearity information is calculated by measuring the amplitude of the 20 KHz sinusoid as per (15). With a sampling frequency of 1.28MHz, it takes only 128 clock cycles to measure the amplitude from a single cycle of the sinusoid.…”

“…Large systems used in networking/communication, imaging, computation and biomedical applications, which used to be bulky and complex, are now being shrunk into miniature SoCs [12][13][14][15][16]. It is commendable that researchers have successfully extended Moore's law towards the fundamental limits.…”

“…15 shows the distribution of SNDR/SFDR with the mismatch between replica and signal VCOs.Special layout techniques have to be adopted to keep the mismatch to its minimum.Delay cells with tunable load capacitances, as shown inFigure 3.7, could be used to adjust the delay to reduce any mismatch between VCOs. 100 Monte-Carlo runs for mismatch between signal VCO and replica VCO Effect of VCO-phase noise on output SNR VCO phase noise affects the in-band noise of a VCO-based ADC considerably, hence design parameters for VCO should be carefully considered.…”

“…18 shows the 215 -point FFT plots of output averaged 16 times before and after calibration for an input sinusoid of frequency little higher than 1.8 KHz and amplitude 300mVPP. It could be seen from the figure that third order distortions improved by more than 21dB and the SNDR improved from 42dB to 55dB.…”