6.6 A 22.5-to-32Gb/s 3.2pJ/b referenceless baud-rate digital CDR with DFE and CTLE in 28nm CMOS

A 1.8-pJ/b, 12.5–25-Gb/s Wide Range All-Digital Clock and Data Recovery Circuit

“…This increases the power consumption and chip area: e.g. the work in [4], which includes a CTLE and a DFE, has an area which is 10 times larger than our work. Additionally, the power consumption per bit is more than 75 % higher than our work.…”

“…E.g. the jitter tolerance can easily be set such that it satisfies the STM-256 mask and exceeds the jitter tolerance of [2] and [4]. Please note that for the lower jitter frequencies, the jitter tolerance is better than indicated on the figures, since the highest jitter level that our equipment can generate still leads to a BER that is better than 10 -12 .…”

“…27(a) and Fig. 27 Persistence plots of (a) the recovered (differential) clock (jitter < 1.5 psrms) and (b) the recovered data (jitter ≈ 3.71 psrms) tolerance of [2] and [4] are added for comparison. These jitter tolerance curves are measured by applying a PRBS7 input data sequence at 25 Gb/s with sinusoidal jitter.…”

“…so-called All-Digital Clock and Data Recovery (AD-CDR) circuits. ADCDRs are derived from the first All-Digital Phase Locked Loop (AD-PLL) introduced in [13] and comprise a phase detector and a digital controlled oscillator in addition to a digital loop filter [2]- [4], [14]- [18]. PLL-based CDR circuits have the advantage over alternative digital friendly CDRs that they have intrinsically a wide frequency capture range due to the ability to adapt both phase and frequency [19].…”

“…There is only one very recent related work [4] where the digital block is entirely synthesized. To accommodate this synthesis, the input of the digital loop is heavily demultiplexed into many parallel lanes but this has disadvantages: a large amount of parallel samplers are needed to process the highspeed data input and this in turn requires a considerable clock distribution network.…”