5 Gbps Radiation-Hardened Low-Power Pulse Serial Link

Miller, Mary K.; Magazzù, G.; Brewer, Forrest

doi:10.1109/tns.2015.2507551

Cited by 4 publications

(2 citation statements)

References 20 publications

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“…The oscillator design is a transmission line ring with 16 buffering points folded so that the speed of light delay along the TM-line is matched to the buffer delay between the folded access points. In contrast to previous work, the buffer elements are very non-linear pulse-gates [4] that sense a rising edge on input and output a pulse. By design, the buffer is insensitive to both the pulse width and amplitude once a threshold is met and the pulse-shape lowers the active duty cycle of the oscillator.…”

Section: A Oscillator Topologymentioning

confidence: 96%

Low phase noise pulse rotary wave voltage controlled oscillator

Miller

Dalakoti

Mukim

et al. 2017

2017 International SoC Design Conference (ISOCC)

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This paper presents a low phase noise, wide tuning range voltage controlled oscillator. The oscillator uses a rotary wave oscillator topology, with pulse regenerative gates used as amplifiers. Pulse gates confer a paticular low-duty cycle pulse waveform whose arrival time is very weakly dependent on amplitude or pulse width. This reduces the root mean square value of Impulse Sensitivity Function, thereby reducing the phase noise. Further, the oscillator rejects common mode supply noise by double inversion of signals in every stage. Timing signals are ground referenced so the supply can be used as a control voltage. The fabricated 2.96 GHz oscillator in GFUS8RF(130nm) has phase noise of -132.2dBc/Hz @ 10MHz offset. The oscillator has a tuning range of 2.64GHz to 2.96GHz with average phase noise of -130.71dBc/Hz @ 10MHz offset.

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Section: A Oscillator Topologymentioning

confidence: 96%

Low phase noise pulse rotary wave voltage controlled oscillator

Miller

Dalakoti

Mukim

et al. 2017

2017 International SoC Design Conference (ISOCC)

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“…This oscillator is based on pulse-gates which have high timing repeatability and have been used in high performance serial links [1]. The design of the circuit results in sensitivity only to the rising edge rate (not the amplitude or pulse width once the trigger threshold is reached).…”

Section: Introductionmentioning

confidence: 99%

High performance pulse ring voltage controlled oscillator for Internet of Things

Dalakoti

Miller

Brewer

2017

2017 International SoC Design Conference (ISOCC)

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This paper presents a low phase noise, low power, wide tuning range, small area pulse ring oscillator fabricated in inexpensive 130nm CMOS technology, suitable for the widescale internet of things market. The ring uses very non-linear Pulse gates instead of conventional inverters as buffers substantially reducing the impulse sensitivity function (ISF) and thus the phase noise. The timing signal is rising-edge and ground referenced, allowing the supply to be used as control voltage. Common mode supply noise is rejected by double inversion in every stage of of the pulse gate as well as insensitivity to pulse amplitude and width. Fabricated ring oscillators show a phase noise of -98.41 dBC/Hz at 1MHz offset for 1.872GHz oscillator at 2.94mW power consumption and -95.14dBC/Hz at 1MHz offset for 388MHz oscillator at 216uW power consumption. The oscillators have a tuning range of 388MHz to 2.455GHz.

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