4K-cells Resistive and Charge-Base-Capacitive Measurement Test Structure Array (R-CBCM-TSA) for CMOS Logic Process Development, Monitor and Model

Abstract

To maximize the design efficiency of the test chip area and maintain the high accuracy measurement requirement of resistors and capacitors, a 4K-cells resistive and charge-base capacitive test structure array is designed for CMOS logic process development, monitor and model. The test chip utilizes 4-terminal (one of 4 is strongly grounded) Kelvin force/sense measurement for resistive-type and charge-base capacitance measurement (CBCM) for capacitive-type test structures. With the aid of memory-addressing design scheme, any one of the device-under-test in an array can be randomly or sequentially selected for testing with all of them sharing a common probe pad group. To accelerate the testing speed, the address control signals of 8 test structure array are connected in parallel for synchronized parallel testing. A 32x16x8 test structure array has been implemented by utilizing a state-of-the-art logic process to demonstrate design feasibility. The results confirm the excellence of this architecture in measurement with 0.1fF for capacitive and 0.1ohm for resistive systematic errors, and 7 times testing speed improvement.

Impact of Process Variations and Defects on RF Front-end in Nanoscale CMOS

“…CBCM for measuring capacitance [2] is first proposed by Chen, J. C., Sylvester, D. and Chenming Hu at UC Berkeley in 1998. Many improving circuits were proposed to enhance the measuring accuracy in recent years [3][4][5][6]. The traditional CBCM circuit consists of two pseudo inverters shown in Fig.…”