2014
DOI: 10.1109/tmtt.2014.2317551
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45-nm CMOS SOI Technology Characterization for Millimeter-Wave Applications

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Cited by 85 publications
(20 citation statements)
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“…3(b). The interconnect parasitics are much better than CMOS transistors, which typically reduce f t / f max from 460 GHz (referred to M1) to 260 GHz (referred to top metal) [37]. The better performance is due to the all-copper backend and the thick dielectrics used in the IBM 9HP process.…”
Section: Technologymentioning
confidence: 99%
“…3(b). The interconnect parasitics are much better than CMOS transistors, which typically reduce f t / f max from 460 GHz (referred to M1) to 260 GHz (referred to top metal) [37]. The better performance is due to the all-copper backend and the thick dielectrics used in the IBM 9HP process.…”
Section: Technologymentioning
confidence: 99%
“…with a single emitter finger, dual collector, and base fingers (C-B-E-B-C) results in a peak f t / f max of 310/350 GHz at 1.5-2.5 mA/μm bias current when referred to M1 (Metal 1) [38], and f t / f max drops to 260/300 GHz when referred to the top metal LD due to the interconnection parasitics [28], [39]. This is much better than the CMOS transistors which typically reduce f t / f max from 460 GHz (referred to M1) to 260 GHz (referred to the top metal) [40]. The better performance is due to the all-copper backend and the thick dielectrics used in the IBM 9HP process.…”
Section: Technologymentioning
confidence: 99%
“…In this paper, we take into account the full models of the transistors of a process design kit commercially available, which adopts the BSIM4v4 model including their parasitic components and second order effects. In compliance with the expectations from the theoretical study, in our analyses, we will exclude the effects of the layout interconnections that introduce additional parasitic components, unwanted coupling, and other proximity effects, which can be minimized by careful layout and estimated through electromagnetic and parasitic extraction tools according to latest advanced design approach for high‐frequency integrated circuits on silicon . Moreover, it is worth considering that the additional parasitic components introduced by the layout could lead to an unjustified increase of complexity and cumbersome expressions that could mask the inherent topological properties that we would like bringing to the light in our study.…”
Section: Introductionmentioning
confidence: 98%
“…layout and estimated through electromagnetic and parasitic extraction tools according to latest advanced design approach for high-frequency integrated circuits on silicon [8,9]. Moreover, it is worth considering that the additional parasitic components introduced by the layout could lead to an unjustified increase of complexity and cumbersome expressions that could mask the inherent topological properties that we would like bringing to the light in our study.…”
Section: Introductionmentioning
confidence: 99%