4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

Turner, S.E.; Elder, R.; Jansen, D.; Kotecki, David E.

doi:10.1109/lmwc.2005.844199

Cited by 18 publications

(8 citation statements)

References 6 publications

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“…The accumulator could be extended to be 48-bit when a high resolution DDFS is required. 0.25 m CMOS [3] 90 nm CMOS [4] InP DHBT [10] SiGe HBT [11] GaAs HBT (This work) …”

Section: Resultsmentioning

confidence: 99%

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Chen

Zhou

et al. 2012

Chin. Sci. Bull.

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A 32-bit pipeline accumulator with carry ripple topology is implemented for direct digital frequency synthesizer. To increase the throughout while hold down the area and power consumption, a method to reduce the number of the pre-skewing registers is proposed. The number is reduced to 29% of a conventional pipeline accumulator. The propagation delay versus bias current of the adder circuit with different size transistors is investigated. We analyze the delay by employing the open circuit time constant method. Compared to the simulation results, the maximum error is less than 8%. A method to optimum the design of the adder based on the propagation delay is discussed. The clock traces for the 32-bit adder are heavily loaded, as there are 40 registers being connected to them. Moreover, the differential clock traces, which are much longer than the critical length, should be treated as transmission lines. Thus a clock distribution method and a termination scheme are proposed to get high quality and low skew clock signals. A multiple -type termination scheme is proposed to match the transmission line impedance. The 32-bit accumulator was measured to work functionally at 5.3 GHz. Direct digital frequency synthesizer (DDFS) is able to generate sinusoids with sub-hertz resolution, good spectral purity, fast frequency switching and phase continuity on switching. For the next generation radar and communication systems, DDFS operating at GHz-range clock is required. However, the operating speed of DDFS is limited by the phase accumulator (PA), which consumes large area and power. Many architectures and designs have been reported in the literature for the PA in DDFS, such as the carry-ripple adder (RCA) [1], the carry look ahead adder (CLA) [2] and the pipelined adder [3,4]. Though faster than RCA, the significant fan-in and fan-out requirements of CLA architecture lead to lower clock rate as the bit width increases. The pipeline accumulator offers significant speed improvement compared to the CLA, which has large propagation delays before a valid sum is produced. The carry ripple pipeline accumulator is more practically suitable for GHz DDFS with 32-bit resolution in terms of compact layout and hardware implementation. A 32-bit pipeline accumulator with 8-stage pipeline is illustrated in Figure 1. A number of pre-skewing and deskewing registers are required to keep the input and output of the accumulator coherent. To minimize the area while achieving the desired operating speed, a new hardware efficient PA is proposed in this work. This method reduces the number of registers required in the pipeline without performance degradation. The optimum design in terms of power and propagation delay is investigated. The clock for the accumulator is critical for high speed operation. A clock distribution method and a termination scheme are proposed.

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“…The accumulator could be extended to be 48-bit when a high resolution DDFS is required. 0.25 m CMOS [3] 90 nm CMOS [4] InP DHBT [10] SiGe HBT [11] GaAs HBT (This work) …”

Section: Resultsmentioning

confidence: 99%

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Chen

Zhou

et al. 2012

Chin. Sci. Bull.

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“…In this DDS design, the accumulator is the limiting factor for speed, so the maximum operating frequency of the DDS is constrained to 13 GHz. While this single clock cycle accumulator is slower than previously reported accumulators [5], [6], it is advantageous because it contains fewer pipeline registers. This greatly reduces the power consumption, while also simplifying clock distribution of the circuit.…”

Section: A Phase Accumulatormentioning

confidence: 88%

“…Unlike previously reported high speed accumulators [5], [6], where pipelining is utilized to compute the accumulation over multiple clock cycles, the accumulator in this design computes the entire 8-b accumulation operation in a single clock cycle. As shown in Fig.…”

Section: A Phase Accumulatormentioning

confidence: 99%

“…Extending the 4-b, 41-GHz accumulator [5] to 8-b, would lead to an estimated power consumption of 7.86 W, with two 4-b accumulator blocks at 2.86 W each and a 4-b register block at 2.12 W. Likewise, an extension of the reduced power accumulator [6] to 8-b is estimated to result in a power consumption of 6.39 W with 2.38 W from each of the 4-b accumulators and 1.63 W from the 2-b register. By comparison, the 8-b accumulator in this design uses only 2.13 W with a maximum simulated operating frequency of 13 GHz.…”

Section: A Phase Accumulatormentioning

confidence: 99%

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Direct digital synthesizer with ROM-Less architecture at 13-GHz clock frequency in InP DHBT technology

Turner

Kotecki

2006

IEEE Microw. Wireless Compon. Lett.

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A direct digital synthesizer (DDS) implemented in InP double heterojunction bipolar transistor (DHBT) technology is reported. The DDS has a ROM-less architecture and instead uses digital logic for phase conversion. The DDS operates up to a 13 GHz clock rate and is capable of synthesizing output frequencies up to 6.5 GHz. Measured spurious free dynamic range (SFDR) ranged from 34 dBc at low frequency control words (FCWs) to 26.67 dBc at high FCWs. The test circuit is implemented with 1646 transistors and consumes 5.42 W of power. Index Terms-Accumulator, digital to analog converter (DAC), direct digital synthesizer (DDS), heterojunction bipolar transistor (HBT), high-speed integrated circuits (ICs), Indium Phosphide (InP).

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“…A 4-bit adder-accumulator was implemented in InP DHBT technology with a 41 GHz sampling rate, enabling Direct Digital Synthesis (DDS) of up to 10 GHz bandwidth [15]. High speed Analog-to-Digital Converters (ADCs) are also implemented in InP HBTs with 1.8-bit resolution at 20 GS/s in a flash configuration [16] and 3.9-bit resolution at 10 GS/s with 4.9 GHz input bandwidth [17].…”

Section: High Performance Digital and Mixed-mode Icsmentioning

confidence: 99%

Recent Advances in III-V Electronics

Chen¹,

Baeyens²,

Weimann³

et al. 2006

IEEE Custom Integrated Circuits Conference 2006

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Compound III-V semiconductor circuits promise fast and power efficient analog, digital and mixed-mode applications. This paper will provide an overview of recent advances in high speed III-V compound devices and integrated circuits for high capacity wireless and optic fiber communications. Several critical compound semiconductor ASIC technologies and their unique performance advantages over prevailing silicon CMOS and SiGe technologies will be illustrated.

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4-bit adder-accumulator at 41-GHz clock frequency in InP DHBT technology

Cited by 18 publications

References 6 publications

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

A 5.3-GHz 32-bit accumulator designed for direct digital frequency synthesizer

Direct digital synthesizer with ROM-Less architecture at 13-GHz clock frequency in InP DHBT technology

Recent Advances in III-V Electronics

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