3D-TTN: a power efficient cost effective high performance hierarchical interconnection network for next generation green supercomputer

Abstract

Green computing is an important factor to ensure the eco-friendly use of computers and their resources. Electric power used in a computer converts into heat and thus, the system takes fewer watts ensuring less cooling. This lower energy consumption allows to be less costly to run as well as reduces the environmental impact of powering the computer. One of the most challenging problems for the modern green supercomputers is the reduction of current power consumptions. Consequently, regular conventional interconnection networks also show poor cost performance. On the other hand, hierarchical interconnection networks (like-3D-TTN) can be a possible solution to those issues. The main focus for this paper is the estimation of power usage at the on-chip level for 3D-TTN with the various other networks along with the analysis of static network performance. In our analysis, 3D-TTN requires about 32.48% less router power usage at the on-chip level and can also achieve near about 21% better diameter performance as well as 12% better average distance performance than the 5D-Torus network. Similarly, it also requires only about 14.43% higher router power usage; however, can achieve 23.21% better diameter performance and 26.3% better average distance than recent hierarchical interconnection network- 3D-TESH. The most attractive feature of this paper is the static hop distance parameter and per watt analysis (power-performance). According to our power-performance results, 3D-TTN can also show better result than the 3D-Mesh, 2D-Mesh, 2D-Torus and 3D-TESH network even at the lowest network level. Moreover, this paper is also featured with the static effectiveness analysis, which ensures cost and time efficiency of 3D-TTN.

Cost-effectiveness analysis of a shifted completely connected network for massively parallel computer systems

“…The number of the communication links is a function of the number of the processors as in Equation (5).…”

“…A parallel computing system is a collection of processing elements that cooperate and communicate to solve large problems fast [3]. These systems are the highest level of computing designed to manipulate high bandwidth in a parallel and short time and to solve many difficult problems in many areas such as bioscience, chemistry, geology, physics, engineering, and computer science [4].Supercomputers also can be used in smart cities, food safety examinations, optimize energy production, and reply to emergency situations [5]. To achieve high-performance computing, thousands of powerful CPUs are used to reach high-end computing by creating massively parallel computer systems (MPC) [3] [6].…”

An Extensive Power and Performance Analysis for High Dimensional Mesh and Torus Interconnection Networks

“…It can be explained as the designing, using, and disposing of computing equipment in a way to minimize their environmental impact (Green500 List, n.d.;Vikram, 2015). Low energy consumption not only helps to minimize the running cost but also reduces the environmental impact of powering the computer (Al Faisal et al, 2021;Pavlidis & Friedman, 2007). In 2016, the many-core accelerators PEZY-SCnp at RIKEN achieved 6673.8MFLOPS/w power efficiency (Fu, 2016).…”

“…Finally, this research paper is immensely important for the field of interconnection networks due to the design consideration of on-chip as well as off-chip networks based on for conventional networks like-Mesh and Torus, especially for the hierarchical networks where on-chip levels are often considered as high degree networks and off-chip networks are considered as low degree networks in order to reduce the power consumptions. For example, 3D-TTN network (Al Faisal et al, 2021) considers the 3D Torus network for its on-chip module and the 2D Torus network for its off-chip connectivity. Similarly, a latest hierarchical interconnection network specially designed for exascale supercomputers named as Hierarchical Flattened Butterfly Network (HFBN) considers similar to 2D flattened butterfly architecture at the NoC level and the upper level is designed with 2D Torus network (Faisal et al, 2022).…”

A Novel Tradeoff Analysis between Traffic Congestion and Packing Density of Interconnection Networks for Massively Parallel Computers

“…HINs have been adequately described in the literature as a revolutionary milestone for massively parallel computers and nest-generation parallel computing. For instance, the extended hypercube [13], Tori-connected mesh (TESH) [14], hierarchical torus network (HTN) [15], rectangular twisted torus meshes (RTTM) [16], midimew connected mesh network (MMN) [17,18], hierarchical Tori connected mesh network (HTM) [19], shifted completely connected network (SCCN) [20], 3-dimensional Tori connected torus network (3D-TTN) [21], and many more networks have been proposed and assessed in recent years as a means to promote MPC systems. The numerous works pertinent to the HIN is testament to its numerous benefits in terms of network performance and computational speed.…”