3D on-chip memory for the vector architecture

Funaya, Yusuke; Egawa, Ryusuke; Takizawa, Hiroyuki; Kobayashi, Hiroaki

doi:10.1109/3dic.2009.5306537

Cited by 4 publications

(2 citation statements)

References 16 publications

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“…However, there are several researches designing 3-D stacked cache memories, which realize a high memory bandwidth and huge capacity using TSVs [14] [15]. Since TSVs have a small RC delay compared to conventional 2D wires, and recent TSVs process technologies allow to implement many TSVs on a chip [16] 3-D stacked cache memories have potential to realize higher memory bandwidth compared to 2-D implementation [17]. Thus, in this section, we can assume the future 3-D stacked vector cache have a high memory bandwidth of 128GB/sec per core and 256GB/sec per core.…”

Section: Discussionmentioning

confidence: 99%

Effects of 3-D stacked vector cache on energy consumption

Egawa

Funaya

Nagaoka

et al. 2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

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To realize a high computational efficiency, a 3-D stacked chip multi-vector processor (CMVP) has been proposed. However, the 3-D stacked CMVP has not been evaluated well in terms of energy consumption. Therefore, to clarify the potential of the 3-D stacked CMVP, this paper evaluates and analyzes the energy consumption of the 3-D stacked CMVP using real scientific applications. Especially, this paper focuses on the energy reduction effects given by a large scale vector cache, which can be realized by 3-D die stacking technologies. The evaluation results show the vector cache on the 3-D stacked CMVP has enough potential to achieve a low energy and high performance processing of the cutting edge scientific applications.

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Section: Discussionmentioning

confidence: 99%

Effects of 3-D stacked vector cache on energy consumption

Egawa

Funaya

Nagaoka

et al. 2012

2011 IEEE International 3D Systems Integration Conference (3DIC), 2011 IEEE International

Self Cite

View full text Add to dashboard Cite

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“…A storage dependency is a type of resource creation and provision dependency that is specific to memory, both on-chip and off-chip. Storage dependencies can be mitigated by implementing the storage in the control plane [8,16,29,35]. …”

Section: Resource Creation and Provision Contentionmentioning

confidence: 99%