3D NAND Flash Status and Trends

Heineck, Lars; Liu, Jin

doi:10.1109/imw52921.2022.9779282

Cited by 24 publications

(8 citation statements)

References 12 publications

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“…10) Additionally, the total number of memory layers in current 3D NAND is already >200, and expected to increase further, 11) requiring a corresponding increase of the HV peri devices. This poses significant challenges to the area consumption due to HV devices, and even the expected introduction of the wafer to wafer bonding approach 11,12) will not solve it.…”

Section: Introductionmentioning

confidence: 99%

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Spessot,

Matagne,

Arimura

et al. 2024

Jpn. J. Appl. Phys.

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We propose for the first time a dedicated FinFET (FF) technology with specific optimization for tox>40nm and lateral break-down (LBD)>35V to replace the conventional planar high voltage (HV) transistors in the 3D NAND Flash periphery. We show significant current increase (>x2) and area saving per footprint, solving one of the key bottlenecks of future 3D NAND nodes. Fabrication of thermally stable prototypes is shown, with no significant impact on the overall fabrication complexity

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Section: Introductionmentioning

confidence: 99%

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Spessot,

Matagne,

Arimura

et al. 2024

Jpn. J. Appl. Phys.

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“…A complete NAND flash memory chip is mainly composed of flash memory particles and CMOS peripheral circuits. At present, the construction of CMOS peripheral circuits mainly includes the following three ways: CMOS next Array (CnA) [1], [2], CMOS under array (CuA) [3], [4] and Xtacking [5], [6]. But no matter which way it is, the NAND flash array and peripheral circuits need to be prepared on different layers and by different processes.…”

Section: Introductionmentioning

confidence: 99%

Transparent Multi-Level NAND Flash Memory and Circuits Based on ZnO Thin Film Transistor

Zhang

Zhao

Chong

et al. 2023

IEEE Electron Device Lett.

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“…With the continuous development of smartphones, 5G, artificial intelligence, and cloud computing, the demand for higher bit density in the market has grown rapidly. The bit density is generally increased by stacking more layers in 3D NAND Flash [ 1 , 2 , 3 , 4 , 5 , 6 , 7 , 8 , 9 ]. However, the connection scheme of using a body contact spacer (BCS) between channel polysilicon and the array common source line faces challenges during the process of removing the bottom of the gate stack, especially when stacking more than two stacks due to the overlap problem [ 10 ].…”

Section: Introductionmentioning

confidence: 99%

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

et al. 2023

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The bit density is generally increased by stacking more layers in 3D NAND Flash. Gate-induced drain leakage (GIDL) erase is a critical enabler in the future development of 3D NAND Flash. The relationship between the drain-to-body potential (Vdb) of GIDL transistors and the increasing number of layers was studied to explain the reason for the self-adaption of the GIDL erase. The dynamics controlled by the drain-to-body and drain-to-gate potential contribute to the self-adaption of the GIDL erase. Increasing the number of layers leads to a longer duration of the maximum value of Vdb (Vdb_max), combined with the increased drain-to-gate potential, which enhances the GIDL current and further boosts channel potential to reach the same value at different positions of the NAND string. We proposed a method based on the correlation between the duration of Vdb_max and the number of layers to obtain the limited layers of the GIDL erase. The limited layers allowed are more than four times the number of layers used in the current simulation. Combining the novel method of dividing the channel into multi-regions with the asynchronous GIDL erase method will be useful for further stacking more layers in 3D NAND Flash.

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3D NAND Flash Status and Trends

Cited by 24 publications

References 12 publications

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Compact thermally stable high voltage FinFET with 40 nm tox and lateral break-down >35 V for 3D NAND flash periphery application

Transparent Multi-Level NAND Flash Memory and Circuits Based on ZnO Thin Film Transistor

Self-Adaption of the GIDL Erase Promotes Stacking More Layers in 3D NAND Flash

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