3D Investigation of 8-nm Tapered n-FinFET Model

Boukortt, Nour El Islam; Patanè, Salvatore; Crupi, Giovanni

doi:10.1007/s12633-019-00253-y

Cited by 13 publications

(8 citation statements)

References 17 publications

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“…Because of aggressive technology scaling, the channel length of silicon transistors is currently smaller than 8 nm. 1 High leakage current in silicon transistors [2][3][4] at smaller technologies leads to sub-threshold swing of up to 60 mV decade À1 . 5 Two-dimensional (2D) transition metal dichalcogenides (TMDs) have demonstrated their promising semiconducting and optical properties.…”

Section: Introductionmentioning

confidence: 99%

Effect of gamma irradiation on the physical properties of MoS₂ monolayer

Chavda¹,

Srivastava²,

Vaughan³

et al. 2023

Phys. Chem. Chem. Phys.

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Section: Introductionmentioning

confidence: 99%

Effect of gamma irradiation on the physical properties of MoS₂ monolayer

Chavda¹,

Srivastava²,

Vaughan³

et al. 2023

Phys. Chem. Chem. Phys.

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“…The Hafnium Oxide (𝐻𝑓𝑂 2 ) has a band gap of 5.3-5.7 eV and can behave as a dielectric insulator. HfO2 has high dielectric constant, great thermal stability and also lower values of leakage current [7]. The Novel device structure simulated is of n-type with 5.0 × 10 18 (𝑐𝑚 −3 ) doping concentration for all the regions of source, drain and channel.…”

Section: Introductionmentioning

confidence: 99%

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Gangwani

Hajela

2022

IOP Conf. Ser.: Mater. Sci. Eng.

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This paper depicts the analog investigation of a Novel Stacked Oxide Top Bottom Gated Junctionless (TBG-JL) Fin-shaped Field Effect Transistor (FinFET) structure. The structure is designed in this way to enhance the switching performance and curtail the Short Channel Effects (SCEs). The study is done on Silvaco Atlas TCAD tools for the Novel Stacked Oxide FinFET device and analyzed against Top-Bottom Gated Junctionless FinFET and Traditional FinFET. The Novel device shows 280 times improvement in switching ratio when stacked against the Traditional JL FinFET at identical gate length at room temperature (300K). The results from device simulation affirm that the Novel device has better analog performance over Traditional Junctionless FinFET and diminishes the Short Channel Effects (SCEs) a cut above the Traditional Junctionless FinFET.

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“…In the silicon industry, device miniaturization is still considered a key feature to achieve better short-channel performance. Currently, a great effort concerns the development of FinFET devices with dimensions below 5 nm that represent the target in the near future [4][5][6][7][8]. Despite the effort made to create devices with dimensions below 5 nm, many aspects still remain to be clarified and optimized, also with a view to a larger-scale application of the devices.…”

Section: Introductionmentioning

confidence: 99%

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

et al. 2021

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The FinFET architecture has attracted growing attention over the last two decades since its invention, owing to the good control of the gate electrode over the conductive channel leading to a high immunity from short-channel effects (SCEs). In order to contribute to the advancement of this rapidly expanding technology, a 3D 14-nm SOI n-FinFET is performed and calibrated to the experimental data from IBM by using Silvaco TCAD tools. The calibrated TCAD model is then investigated to analyze the impact of changing the fin width, fin height, gate dielectric material, and gate length on the DC and RF parameters. The achieved results allow gaining a better understanding and a deeper insight into the effects of varying the physical dimensions and materials on the device performance, thereby enabling the fabrication of a device tailored to the given constraints and requirements. After analyzing the optimal values from different changes, a new device configuration is proposed, which shows a good improvement in electrical characteristics.

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3D Investigation of 8-nm Tapered n-FinFET Model

Cited by 13 publications

References 17 publications

Effect of gamma irradiation on the physical properties of MoS₂ monolayer

Effect of gamma irradiation on the physical properties of MoS₂ monolayer

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

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3D Investigation of 8-nm Tapered n-FinFET Model

Cited by 13 publications

References 17 publications

Effect of gamma irradiation on the physical properties of MoS2 monolayer

Effect of gamma irradiation on the physical properties of MoS2 monolayer

Analog Performance Analysis of a Novel 5nm Stacked Oxide Top Bottom Gated Junctionless FinFET

Effects of Varying the Fin Width, Fin Height, Gate Dielectric Material, and Gate Length on the DC and RF Performance of a 14-nm SOI FinFET Structure

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Effect of gamma irradiation on the physical properties of MoS₂ monolayer

Effect of gamma irradiation on the physical properties of MoS₂ monolayer