3D integration technology for set-top box application

Henry, David D.; Chéramy, S.; Charbonnier, Jean; Chausse, P.; Neyret, M.; Brunet-Manquat, C.; Verrun, S.; Sillon, N.; Bonnot, L.; Gagnard, X.; Saugier, E.

doi:10.1109/3dic.2009.5306561

Cited by 15 publications

(2 citation statements)

References 3 publications

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“…The TSV last technology is very flexible and can be applied to many domains and applications [3]. A simplified process flow diagram is presented in figure 8.…”

Section: Technology Descriptionmentioning

confidence: 99%

3D integration technology for hybrid pixel detectors designed for particle physics and imaging experiments

Henry

Berthelot

Cuchet

et al. 2012

2012 4th Electronic System-Integration Technology Conference

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Hybrid pixel detectors are now widely used in particle physics experiments and are becoming established at synchrotron light sources. They have also stimulated growing interest in other fields and, in particular, in medical imaging. Through the continuous pursuit of miniaturization in CMOS it has been possible to increase the functionality per pixel while maintaining or even shrinking pixel dimensions. The main constraint on the more extensive use of the technology in all fields is the cost of module building and the difficulty of covering large areas seamlessly.On another hand, in the field of electronic component integration, a new approach has been developed in the last years, called 3D Integration. This concept, based on using the vertical axis for component integration, allows improving the global performance of complex systems. Thanks to this technology, the cost and the form factor of components could be decreased and the performance of the global system could be enhanced. In the field of radiation imaging detectors the advantages of 3D Integration come from reduced inter chip dead area even on large surfaces and from improved detector construction yield resulting from the use of single chip 4-side buttable tiles. For many years, numerous R&D centres and companies have put a lot of effort into developing 3D integration technologies and today, some mature technologies are ready for prototyping and production.The core technology of the 3D integration is the TSV (Through Silicon Via) and for many years, LETI has developed those technologies for various types of applications.In this paper we present how one of the TSV approaches developed by LETI, called TSV last, has been applied to a readout wafer containing readout chips intended for a hybrid pixel detector assembly. In the first part of this paper, the 3D design adapted to the read-out chip will be described. Then the complete process flow will be explained and, finally, the test strategy adopted and the test results obtained will be discussed. Some prospects for the next steps of the project will be also described at the end.

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“…The TSV last technology is very flexible and can be applied to many domains and applications [3]. A simplified process flow diagram is presented in figure 8.…”

Section: Technology Descriptionmentioning

confidence: 99%

3D integration technology for hybrid pixel detectors designed for particle physics and imaging experiments

Henry

Berthelot

Cuchet

et al. 2012

2012 4th Electronic System-Integration Technology Conference

Self Cite

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“…The two layers are linked together through microbumps (Copper Pillars [10]). This approach avoids the classical limitation of area when eFPGA is embedded inside the same silicon layer.…”

Section: B Global Architecturementioning

confidence: 99%

Towards future adaptive multiprocessor systems-on-chip: An innovative approach for flexible architectures

Lemonnier

Millet

Almeida

et al. 2012

2012 International Conference on Embedded Computer Systems (SAMOS)

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Abstract-This paper introduces adaptive techniques targeted for heterogeneous manycore architectures and introduces the FlexTiles platform, which consists of general purpose processors with some dedicated accelerators. The different components are based on low power DSP cores and an eFPGA on which dedicated IPs can be dynamically configured at run-time. These features enable a breakthrough in term of computing performance while improving the on-line adaptive capabilities brought from smart heuristics. Thus, we propose a virtualisation layer which provides a higher abstraction level to mask the underlying heterogeneity present in such architectures. Given the large variety of possible use cases that these platforms must support and the resulting workload variability, offline approaches are no longer sufficient because they do not allow coping with time changing workloads. The upcoming generation of applications include smart cameras, drones, and cognitive radio. In order to facilitate the architecture adaptation under different scenarios, we propose a programming model that considers both static and dynamic behaviors. This is associated with self adaptive strategies endowed by an operating system kernel that provides a set of functions that guarantee quality of service (QoS) by implementing runtime adaptive policies. Dynamic adaptation will be mainly used to reduce both overall power consumption and temperature and to ease the problem of decreasing yield and reliability that results from submicron CMOS scales.

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