3D Integration of CMOS transistors with ICV-SLID technology

Wieland, Robert; Bonfert, Detlef; Klumpp, Armin; Merkel, Reinhard; Nebrich, L.; Weber, Josef; Ramm, Peter

doi:10.1016/j.mee.2005.07.052

Cited by 35 publications

(12 citation statements)

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“…Tungsten, on the other hand, has higher stress but has CTE closer to Si [5]. W-fill TSV has been reported for various applications by Malladi et al [1] and Wieland et al [4]. However, detail 3-D stress of W-fill TSV has not been reported.…”

Section: Tungsten Film Stressmentioning

confidence: 99%

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Dao¹,

Triyoso²,

Mora³

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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Thermo-mechanical stress of tungsten-filled (W-fill) through-silicon-via (TSV) is strongly depending on via shape, size and inter-via spacing, which places constraints on TSV design, including 2-D integrated circuit layout and 3-D structure profile. This paper summarizes these constraints and co-relations among thick (up to 1.2μm) tungsten (W) film, W-fill TSV, and surrounding silicon structures, using Flexus bowing measurement, Wright etch method, and also 3-D TSV stress simulations. In this study, the stress was found to be primarily tensile, and tended to be much higher along the longitudinal ends of the TSV compared to the longitudinal side wall. For an isolated TSV of given width and depth: with 30μm length the stress is 45% greater compared to the case of 7μm length. For an array of TSV with given length, width, and depth: larger spacing along the longitudinal axis (length directions) resulted in 35% lower stress at the longitudinal ends of the TSV, while smaller spacing along the transverse axis (width directions) of the TSV resulted in a 46% lower tensile stress. However, along the longitudinal side walls, the tensile stress increases by 200 MPa as the spacing along the transverse axis decreases between neighboring TSV.

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Section: Tungsten Film Stressmentioning

confidence: 99%

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Dao¹,

Triyoso²,

Mora³

et al. 2010

Proceedings of 2010 International Symposium on VLSI Design, Automation and Test

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“…Current computer technology is only 2D, mostly due to limitations in the fabrication processes used to manufacture chips. Current efforts have reached ~2.5D, which means that only 1-3 layers of active devices have been stacked in the z-dimension [2].…”

Section: Attributes 1 and 4: Large Interconnectivity And 3d High Densitymentioning

confidence: 99%

Toward exascale computing through neuromorphic approaches.

James¹

2010

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While individual neurons function at relatively low firing rates, naturally-occurring nervous systems not only surpass manmade systems in computing power, but accomplish this feat using relatively little energy. It is asserted that the next major breakthrough in computing power will be achieved through application of neuromorphic approaches that mimic the mechanisms by which neural systems integrate and store massive quantities of data for real-time decision making. The proposed LDRD provides a conceptual foundation for SNL to make unique advances toward exascale computing. First, a team consisting of experts from the HPC, MESA, cognitive and biological sciences and nanotechnology domains will be coordinated to conduct an exercise with the outcome being a concept for applying neuromorphic computing to achieve exascale computing. It is anticipated that this concept will involve innovative extension and integration of SNL capabilities in MicroFab, material sciences, high-performance computing, and modeling and simulation of neural processes/systems. 4

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“…Table II proposes a comparison between this work and various different 3-D technologies, such as through silicon vias and SiP. Wieland et al [24] report through silicon vias (TSV) with m size and demonstrate that the 3-D process does not affect transistor parameters for a minimum distance TABLE II COMPARISON AMONG VARIOUS DIFFERENT 3-D INTEGRATION APPROACHES between 3-D vias and gates, and thus between 3-D connections and functional circuits, of 11 m [23]. Our work demonstrates the functionality of AC interconnections with an electrode size of m , but our communication approach does not affect substrate parameters and thus adjacent circuits can be as close as allowed by the CMOS technology; so, in our judgment, the pitch enabled by our AC connection is equivalent to the pitch of TSV.…”

Section: Comparison Among Interconnection Technologiesmentioning

confidence: 99%

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities

Fazzi

Canegallo

Ciccarelli

et al. 2008

IEEE J. Solid-State Circuits

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A wireless interconnection scheme based on capacitive coupling provides mono-and bi-directional transmission capabilities for 3-D system integration. Chips are implemented in 0.13 m CMOS technology and assembled face-to-face at die-level. RX-TX circuits are specifically designed for low-power functionality and the implementation takes advantage of the two different voltage thresholds that are available for the standard transistors in the CMOS process we used. The communication circuits are coupled via electrodes with an area down to 8 8 m 2 and this enables the vertical propagation of clock signals at 1.7 GHz, a propagation delay of 420 ps for general purpose signals and a throughput of more than 22 Mb/s m 2 with 0.08 pJ/b energy consumption.

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3D Integration of CMOS transistors with ICV-SLID technology

Cited by 35 publications

References 1 publication

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Thermo-mechanical stress characterization of tungsten-fill through-silicon-via

Toward exascale computing through neuromorphic approaches.

3-D Capacitive Interconnections With Mono- and Bi-Directional Capabilities

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