2005
DOI: 10.1016/j.mee.2005.07.052
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3D Integration of CMOS transistors with ICV-SLID technology

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Cited by 35 publications
(12 citation statements)
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“…Tungsten, on the other hand, has higher stress but has CTE closer to Si [5]. W-fill TSV has been reported for various applications by Malladi et al [1] and Wieland et al [4]. However, detail 3-D stress of W-fill TSV has not been reported.…”
Section: Tungsten Film Stressmentioning
confidence: 99%
“…Tungsten, on the other hand, has higher stress but has CTE closer to Si [5]. W-fill TSV has been reported for various applications by Malladi et al [1] and Wieland et al [4]. However, detail 3-D stress of W-fill TSV has not been reported.…”
Section: Tungsten Film Stressmentioning
confidence: 99%
“…Current computer technology is only 2D, mostly due to limitations in the fabrication processes used to manufacture chips. Current efforts have reached ~2.5D, which means that only 1-3 layers of active devices have been stacked in the z-dimension [2].…”
Section: Attributes 1 and 4: Large Interconnectivity And 3d High Densitymentioning
confidence: 99%
“…Table II proposes a comparison between this work and various different 3-D technologies, such as through silicon vias and SiP. Wieland et al [24] report through silicon vias (TSV) with m size and demonstrate that the 3-D process does not affect transistor parameters for a minimum distance TABLE II COMPARISON AMONG VARIOUS DIFFERENT 3-D INTEGRATION APPROACHES between 3-D vias and gates, and thus between 3-D connections and functional circuits, of 11 m [23]. Our work demonstrates the functionality of AC interconnections with an electrode size of m , but our communication approach does not affect substrate parameters and thus adjacent circuits can be as close as allowed by the CMOS technology; so, in our judgment, the pitch enabled by our AC connection is equivalent to the pitch of TSV.…”
Section: Comparison Among Interconnection Technologiesmentioning
confidence: 99%