3D-Integrated SRAM Components for High-Performance Microprocessors

Puttaswamy, Kiran; Loh, Gabriel H.

doi:10.1109/tc.2009.92

Cited by 53 publications

(33 citation statements)

References 24 publications

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“…3D-integrated SRAM designs can be classified into banked SRAM arrays and multi-ported SRAM arrays [7]. The memory banking technique divides the memory array into multiple sub-modules.…”

Section: D-integrated Sram Structuresmentioning

confidence: 99%

“…A reduction in power consumption can be achieved by dividing the memory array into multiple banks and accessing only the bank that contains the required data. A previous study proposed four different designs of 3D multi-ported SRAM: register partitioning (RP), bit partitioning (BP), port splitting (PS), and hybrid configurations [7].…”

Section: D-integrated Sram Structuresmentioning

confidence: 99%

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An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

Yoon¹,

Park²,

Kim

2015

JSTS:Journal of Semiconductor Technology and Science

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Abstract-As the feature sizes and the operating charges continue to be scaled down, multi-bit soft errors are becoming more critical in SRAM designs of a few nanometers. In this paper, we propose an efficient error detection technique to reduce the size of parity bits by applying a 2D bit-interleaving technique to 3D bit-partitioned SRAM devices. Our proposed bit-interleaving technique uses only 1/K (where K is the number of dies) parity bits, compared with conventional bit-interleaving structures. Our simulation results show that 1/K parity bits are needed with only a 0.024-0.036% detection error increased over that of the existing bit-interleaving method. It is also possible for our technique to improve the burst error coverage, by adding more parity bits.

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“…3D-integrated SRAM designs can be classified into banked SRAM arrays and multi-ported SRAM arrays [7]. The memory banking technique divides the memory array into multiple sub-modules.…”

Section: D-integrated Sram Structuresmentioning

confidence: 99%

Section: D-integrated Sram Structuresmentioning

confidence: 99%

An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

Yoon¹,

Park²,

Kim

2015

JSTS:Journal of Semiconductor Technology and Science

View full text Add to dashboard Cite

show abstract

“…Each bank consists of a complete memory system (i.e., memory cell array, address decoder, write drivers, etc.). An overall reduction in wire length is obtained (about 50 % for certain configurations), resulting into significant reduction in both power and delay [16,18]. A 3D manufactured DRAM based on the stacking of banks manufactured by Samsung is described in [9].…”

Section: D Memory Architecturesmentioning

confidence: 99%

“…The peripheral logic is placed on the bottom layer while the cell array is split across one or multiple layers. This is considered to be the true 3D memory [16]. Research in this area has been performed for both SRAMs [16,25] and DRAMs [2,13].…”

Section: D Memory Architecturesmentioning

confidence: 99%

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Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Taouil

Hamdioui

2012

J Electron Test

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Recent enhancements in process development enable the fabrication of three dimensional stacked ICs (3D-SICs) such as memories based on Wafer-to-Wafer (W2W) stacking. One of the major challenges facing W2W stacking is the low compound yield. This paper investigates compound yield improvement for W2W stacked memories using layer redundancy and compares it to wafer matching. First, an analytical model is provided to prove the added value of layer redundancy. Second, the impact of such a scheme on the manufacturing cost is evaluated. Third, these two parts are integrated to analyze the tradeoff between yield improvement and its associated cost; the realized yield improvement is also compared to yield gain obtained when using wafer matching. The simulation results show that for higher stack sizes layer redundancy realizes a significant yield improvement as compared to wafer matching, even at lower cost. For example, for a stack size of six stacked layers and a die yield of 85 %, a relative yield improvement of 118.79 % is obtained with two redundant layers, while this is 14.03 % only with wafer matching. The additional cost due to redundancy pays off; the cost of producing a good 3D stacked memory chip reduces with 37.68 % when using layer redundancy and only with 12.48 % when using wafer matching. Moreover, the results show that the benefits of layer redundancy become extremely significant for lower die yields. Finally, layer redundancy and wafer matching are integrated to obtain further cost reductions.

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Wafer Stacking and 3D Memory Test

Noia

Chakrabarty

2013

Design-for-Test and Test Optimization Techniques for TSV-based 3D Stacked ICs

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3D-Integrated SRAM Components for High-Performance Microprocessors

Cited by 53 publications

References 24 publications

An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

An Efficient Error Detection Technique for 3D Bit-Partitioned SRAM Devices

Yield Improvement for 3D Wafer-to-Wafer Stacked Memories

Wafer Stacking and 3D Memory Test

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