3D Hardware Canaries

Briais, Sébastien; Caron, Stéphane; Cioranesco, Jean-Michel; Danger, Jean‐Luc; Guilley, Sylvain; Jourdan, Jacques-Henri; Milchior, Arthur; Naccache, David; Porteboeuf, Thibault

doi:10.1007/978-3-642-33027-8_1

Cited by 20 publications

(20 citation statements)

References 10 publications

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“…The time-domain probability that a high-energy particle hits any register during its active time and causes a bit-flip is (12) Then, the total success rate calculated with our prediction model is as (13) The success rate, indicating the probability of a successful ion fault injection for cryptanalysis, out of the experiment is as . The success rate out of the real experiment conforms fairly well to the predicted result out of our proposed model.…”

Section: Success Ratementioning

confidence: 99%

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Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

Shao

et al. 2015

IEEE Trans. Nucl. Sci.

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Transistors hit by heavy ions may conduct transiently, thereby introducing transient logic errors. Attackers can exploit these abnormal behaviors and extract sensitive information from the electronic devices. This paper demonstrates an ion irradiation fault injection attack experiment into a cryptographic field-programmable gate-array (FPGA) circuit. The experiment proved that the commercial FPGA chip is vulnerable to low-linear energy transfer carbon irradiation, and the attack can cause the leakage of secret key bits. A statistical model is established to estimate the possibility of an effective fault injection attack on cryptographic integrated circuits. The model incorporates the effects from temporal, spatial, and logical probability of an effective attack on the cryptographic circuits. The rate of successful attack calculated from the model conforms well to the experimental results. This quantitative success rate model can help evaluate security risk for designers as well as for the third-party assessment organizations. Index Terms-Cryptographic integrated circuits, fault injection, heavy ion, microbeam, single-event transient (SET).

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Section: Success Ratementioning

confidence: 99%

“…State-of-the art FIBs can operate at a precision of 2.5 nm, much less than the gate length of the transistor these days. However, FIB is invasive and becomes infeasible to the chip with a complex metal layer and shield design [13].…”

Section: A Heavy-ion Fault Injectionmentioning

confidence: 99%

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

Shao

et al. 2015

IEEE Trans. Nucl. Sci.

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“…Mesh complexities continue to become increasingly elaborate. In [7], the authors proposed stacking multiple IC dies to effectively integrate a high-density multi-metal-layer active mesh to fully encapsulate the device in the middle.…”

Section: Introductionmentioning

confidence: 99%

Breaking and entering through the silicon

Helfmeier¹,

Nedospasov²,

Tarnovsky

et al. 2013

Proceedings of the 2013 ACM SIGSAC Conference on Computer &Amp; Communications Security - CCS '13

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As the surplus market of failure analysis equipment continues to grow, the cost of performing invasive IC analysis continues to diminish. Hardware vendors in high-security applications utilize security by obscurity to implement layers of protection on their devices. High-security applications must assume that the attacker is skillful, well-equipped and wellfunded. Modern security ICs are designed to make readout of decrypted data and changes to security configuration of the device impossible. Countermeasures such as meshes and attack sensors thwart many state of the art attacks. Because of the perceived difficulty and lack of publicly known attacks, the IC backside has largely been ignored by the security community. However, the backside is currently the weakest link in modern ICs because no devices currently on the market are protected against fully-invasive attacks through the IC backside. Fully-invasive backside attacks circumvent all known countermeasures utilized by modern implementations. In this work, we demonstrate the first two practical fully-invasive attacks against the IC backside. Our first attack is fully-invasive backside microprobing. Using this attack we were able to capture decrypted data directly from the data bus of the target IC's CPU core. We also present a fully invasive backside circuit edit. With this attack we were able to set security and configuration fuses of the device to arbitrary values.

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“…In addition, tailored packaging cannot guarantee resistance against attacks from the reverse side of the chip. Another possibility is to install an active shield on or around the LSI to be protected [3][4][5]. However, the power needed to drive signals through the shield is non-trivial.…”

Section: Introductionmentioning

confidence: 99%

“…However, the power needed to drive signals through the shield is non-trivial. A dynamic active shield surrounding an LSI was first presented in [4]. The new concept of 3D LSI integration is designed to counteract EM attacks exploiting all aspects of the LSI.…”

Section: Introductionmentioning

confidence: 99%

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

et al. 2015

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This paper presents a standard-cell-based semiautomatic design methodology for a new conceptual countermeasure against electromagnetic (EM) analysis and fault-injection attacks. The countermeasure, called the EM attack sensor, utilizes LC oscillators that react to variations in the EM field around a cryptographic LSI caused by a microprobe brought near the LSI. A dual-coil sensor architecture with digital calibration based on lookup table programming can prevent various microprobe-based EM attacks that cannot be thwarted by conventional countermeasures. All components of the sensor core are semiautomatically designed by standard electronic design automation tools with a fully digital standard cell library and hence minimum design cost. This sensor can therefore be scaled together with the cryptographic LSI to be protected. The sensor prototype is designed based on the proposed methodology together with a 128-bit-key composite AES processor in 0.18-µm CMOS with overheads of only 2 % in area, 9 % in power, and 0.2 % in performance, respectively. The countermeasure has been validated against a variety of EM attack scenarios. In particular, some further experimental results are shown for a detailed discussion.

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3D Hardware Canaries

Cited by 20 publications

References 10 publications

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

Heavy-Ion Microbeam Fault Injection into SRAM-Based FPGA Implementations of Cryptographic Circuits

Breaking and entering through the silicon

Design Methodology and Validity Verification for a Reactive Countermeasure Against EM Attacks

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