18th IEEE International Symposium on the Physical and Failure Analysis of Integrated Circuits (IPFA) 2011
DOI: 10.1109/ipfa.2011.5992789
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3D current path in stacked devices: Metrics and challenges

Abstract: 3D current path in stacked devices: Metrics and challenges. Paper presented at the Physical and Failure Analysis of Integrated Circuits (IPFA).

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“…Different techniques have been developed in attempts to constrain and solve such ill-posed inverse problems, including Tikhonov regularization [21], Fourier Filters [17,22], estimation theory [23], probabilistic multi-source reconstructions [22], least square fitting [25,26], Bayesian methods [27], genetic algorithms [28], and direct mapping and fitting in low dimensional systems [29][30][31]. Particularly in the case of failure analysis, previous approaches have tried to sidestep this obstacle by assuming specific geometries and utilizing prior knowledge of the DUT to map 3D current distributions [32][33][34].…”
Section: Figure 5(a)mentioning
confidence: 99%
“…Different techniques have been developed in attempts to constrain and solve such ill-posed inverse problems, including Tikhonov regularization [21], Fourier Filters [17,22], estimation theory [23], probabilistic multi-source reconstructions [22], least square fitting [25,26], Bayesian methods [27], genetic algorithms [28], and direct mapping and fitting in low dimensional systems [29][30][31]. Particularly in the case of failure analysis, previous approaches have tried to sidestep this obstacle by assuming specific geometries and utilizing prior knowledge of the DUT to map 3D current distributions [32][33][34].…”
Section: Figure 5(a)mentioning
confidence: 99%