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Costa, J.C. da; Hoekstra, Jaap; Goossens, M.J.; Verhoeven, C.J.M.; Roermund, Arthur van

doi:10.1023/a:1008372900256

Cited by 15 publications

(3 citation statements)

References 47 publications

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“…, X 72 were presented in sequence to the network to simulate a dynamic behavior, i.e., in the first 1ns time interval X 1 was presented to the network, in the second interval X 2 was presented and so on, totalizing 72ns. This time interval was chosen to fit the roadmap projections (2,3).…”

Section: Simulation Parametersmentioning

confidence: 99%

Image Recognition Task Based on Decoupled Single-Electron Hamming Networks

2007

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This paper presents a black and white image recogniton task implemented using a decoupled single-electron (SET) Hamming neural network. For the first time, more than 18000 single-electron transistors are used in such a task. This network allows a more practical hardware implementation. Simulation results for various temperatures are presented. A vector clustering task is simulated using SIMON. Robustness against random offset charges, as well as dynamic behavior are evaluated.

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Section: Simulation Parametersmentioning

confidence: 99%

Image Recognition Task Based on Decoupled Single-Electron Hamming Networks

2007

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“…Nanoelectronic devices (1,2) are an attractive option for developing GSI (Giga-Scale Integration) or even TSI (Tera-Scale Integration) circuits (3) with dimensions and performance limits (4) beyond ITRS roadmap projections (2). Among nanoelectronic devices, single-electron tunneling (SET) devices based on tunnel junctions (1,5,6,7) present the following features: low power consumption, reduced dimensions and current control.…”

Section: Introductionmentioning

confidence: 99%

Performance Analysis of Single-electron NAND Gates

Silva¹,

Guimarães

2009

ECS Trans.

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In this work, three different circuit architectures implementing single-electron NAND gates are investigated by simulation. A complete behavior analysis of each architecture, considering critical aspects in SET-based circuits, such as co-tunnelling, temperature dependence and offset charges is performed. Power consumption and area estimations (critical for GSI and TSI realizations) are also taken into account.

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“…Nanoelectronic devices (1,2) are an attractive option for developing GSI (Giga-Scale Integration) or even TSI (Tera-Scale Integration) circuits (3) with dimensions and performance limits (4) beyond International Technology Roadmap for Semiconductors (ITRS) projections (2). Among nanoelectronic devices, single-electron tunneling (SET) devices based on tunnel junctions (1,5,6,7) present the following features: low power consumption, reduced dimensions and current control.…”

Section: Introductionmentioning

confidence: 99%