39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation

Farahini, Nasim; Li, Shuo; Tajammul, Muhammad Adeel; Shami, Muhammad Ali; Chen, Guo; Hemani, Ahmed; Wei, Ye

doi:10.1109/iscas.2013.6572129

Cited by 22 publications

(10 citation statements)

References 5 publications

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“…The word synchoros is derived from the Greek word choros for space and is the spatial analog of the well-known concept of synchronicity. This work has been presented in [40] and used to design dedicated hardware for ANNs [41,42], and wireless communication [43].…”

Section: Discussionmentioning

confidence: 99%

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Stathis

Sudarshan

Yang

et al. 2020

J Sign Process Syst

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The Artificial Neural Networks (ANNs), like CNN/DNN and LSTM, are not biologically plausible. Despite their initial success, they cannot attain the cognitive capabilities enabled by the dynamic hierarchical associative memory systems of biological brains. The biologically plausible spiking brain models, e.g., cortex, basal ganglia, and amygdala, have a greater potential to achieve biological brain like cognitive capabilities. Bayesian Confidence Propagation Neural Network (BCPNN) is a biologically plausible spiking model of the cortex. A human-scale model of BCPNN in real-time requires 162 TFlop/s, 50 TBs of synaptic weight storage to be accessed with a bandwidth of 200 TBs. The spiking bandwidth is relatively modest at 250 GBs/s. A hand-optimized implementation of rodent scale BCPNN has been done on Tesla K80 GPUs require 3 kWs, we extrapolate from that a human scale network will require 3 MWs. These power numbers rule out such implementations for field deployment as cognition engines in embedded systems. The key innovation that this paper reports is that it is feasible and affordable to implement real-time BCPNN as a custom tiled application-specific integrated circuit (ASIC) in 28 nm technology with custom 3D DRAM - eBrainII - that consumes 3 kW for human scale and 12 watts for rodent scale. Such implementations eminently fulfill the demands for field deployment.

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Section: Discussionmentioning

confidence: 99%

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Stathis

Sudarshan

Yang

et al. 2020

J Sign Process Syst

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“…The estimated worst-case reconfiguration overhead is 74.9 nJ. [26] (4.1×) [120] 3 Performance/bandwidth used as power is N/A. 4 Estimated for floating-point based on [108].…”

Section: Power and Areamentioning

confidence: 99%

Transmuter

Pal

Feng

Park

et al. 2020

Proceedings of the ACM International Conference on Parallel Architectures and Compilation Techniques

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With the end of Dennard scaling and Moore's law, it is becoming increasingly difficult to build hardware for emerging applications that meet power and performance targets, while remaining flexible and programmable for end users. This is particularly true for domains that have frequently changing algorithms and applications involving mixed sparse/dense data structures, such as those in machine learning and graph analytics. To overcome this, we present a flexible accelerator called Transmuter, in a novel effort to bridge the gap between General-Purpose Processors (GPPs) and Application-Specific Integrated Circuits (ASICs). Transmuter adapts to changing kernel characteristics, such as data reuse and control divergence, through the ability to reconfigure the on-chip memory type, resource sharing and dataflow at run-time within a short latency. This is facilitated by a fabric of lightweight cores connected to a network of reconfigurable caches and crossbars. Transmuter addresses a rapidly growing set of algorithms exhibiting dynamic data movement patterns, irregularity, and sparsity, while delivering GPU-like efficiencies for traditional dense applications. Finally, in order to support programmability and ease-of-adoption, we prototype a software stack composed of low-level runtime routines, and a high-level language library called TransPy, that cater to expert programmers and end-users, respectively. Our evaluations with Transmuter demonstrate average throughput (energy-efficiency) improvements of 5.0× (18.4×) and 4.2× (4.0×) over a high-end CPU and GPU, respectively, across a diverse set of kernels predominant in graph analytics, scientific computing and machine learning. Transmuter achieves energy-efficiency gains averaging 3.4× and 2.0× over prior FPGA and CGRA implementations of the same kernels, while remaining on average within 9.3× of state-of-the-art ASICs. CCS CONCEPTS • Computer systems organization → Reconfigurable computing; Data flow architectures; Multicore architectures.

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“…The static mappers enjoy relaxed processing deadlines. The relaxed processing deadlines allow them to execute complex algorithms such as modulo scheduling [12] [13] and affine loop transformation [14] to efficiently exploit parallelism [15] [16]. Although they find optimal mappings, the compiletime decisions are unable to efficiently cope with unpredictable scenarios found in many real world applications.…”

Section: Related Work and Contributionsmentioning

confidence: 99%

“…2) DRRA interconnection network: We will use the interconnect network of DRRA as a vehicle to quantitatively analyze complexity and overheads of modifying interconnect instructions in CGRAs. The motivation for choosing DRRA network is that it is well documented, its bandwidth has been tested on demanding industrial applications (with Huawei) [14], and we have available all its architectural details from RTL codes to physical design. DRRA hosts a circuit-switched interconnect network.…”

Section: ) Rotation To Offset Generatormentioning

confidence: 99%

“…Table III shows that the remapper (capable to support up to 32 rows) incurs negligible overhead (1.3 % power and 0.2 % area ) compared to DRRA computation layer (containing 14 cells). The motivation for selecting 14 cells for DRRA is that it is the minimum cells needed to support a common CDMA application with Huawei [14]. Of course, to host multiple applications, will require more DRRA cells that will further reduce the comparative hardware overhead incurred by our approach.…”

Section: A Overhead Analysismentioning

confidence: 99%

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RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs

Jafri

Serrano

Iqbal

et al. 2014

2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV)

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Today, Coarse Grained Reconfigurable Architectures (CGRAs) host multiple applications, with arbitrary communication and computation patterns. Compile-time mapping decisions are neither optimal nor desirable to efficiently support the diverse and unpredictable application requirements. As a solution to this problem, recently proposed architectures offer run-time remapping. The run-time remappers displace or expand (parallelize/serialize) an application to optimize different parameters (such as platform utilization). However, the existing remappers support application displacement or expansion in either horizontal or vertical direction. Moreover, most of the works only address dynamic remapping in packet-switched networks and therefore are not applicable to the CGRAs that exploit circuitswitching for low-power and high predictability. To enhance the optimality of the run-time remappers, this paper presents a design framework called Run-time Rotatable-expandable Partitions (RuRot). RuRot provides architectural support to dynamically remap or expand (i.e. parallelize) the hosted applications in CGRAs with circuit-switched interconnects. Compared to state of the art, the proposed design supports application rotation (in clockwise and anticlockwise directions) and displacement (in horizontal and vertical directions), at run-time. Simulation results using a few applications reveal that the additional flexibility enhances the device utilization, significantly (on average 50 % for the tested applications). Synthesis results confirm that the proposed remapper has negligible silicon (0.2 % of the platform) and timing (2 cycles per application) overheads.

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39.9 GOPs/watt multi-mode CGRA accelerator for a multi-standard basestation

Cited by 22 publications

References 5 publications

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

eBrainII: a 3 kW Realtime Custom 3D DRAM Integrated ASIC Implementation of a Biologically Plausible Model of a Human Scale Cortex

Transmuter

RuRot: Run-time rotatable-expandable partitions for efficient mapping in CGRAs

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