36-GHz, 16$\times$6-Bit ROM in InP DHBT Technology Suitable for DDS Application

Manandhar, Sanjeev; Turner, S.E.; Kotecki, David E.

doi:10.1109/jssc.2006.889361

Cited by 8 publications

(6 citation statements)

References 16 publications

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“…As the time to response is proportional to the capacitance and inversely proportional to the current, at a high clock frequency, the parasitic capacitance will not have enough time to respond, causing signal skew. This phenomenon has also been previously reported [11], although it was observed by a bit pattern of "1111111011111110" from a single column. The leakage current of unselected memory cells reduces the current amplitude of the bit lines, and thus the parasitic capacitances on the bit lines require more time to charge and discharge.…”

Section: Simulation Results and Discussionsupporting

confidence: 83%

“…The worst case delay occurs when three of the input bits to the decoder are switched simultaneously [11]. Columns 0 and 4 have the longest delay because all the address bits in the column inputs must be switched simultaneously when going from column 7 to column 0, and from column 3 to column 4, respectively.…”

Section: Simulation Results and Discussionmentioning

confidence: 99%

“…The fastest CMOS ROM reported, operates at a frequency up to 1.1 GHz [9]. A 64-bit, 5-GHz read-write look-up table (LUT) has been implemented in GaAs HBT [10], while an InP HBT 36-GHz, 16×6-bit ROM test circuit has also been fabricated [11], with the output voltage amplitude falling from 330 mV at 20 GHz to 160 mV at 36 GHz.…”

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confidence: 99%

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A 6-GHz ROM suitable for DDFS application in GaAs HBT technology

Chen

Wang²,

et al. 2011

Chin. Sci. Bull.

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Read-only memory (ROM) is widely implemented as a phase-to-amplitude mapping block in direct digital frequency synthesizers (DDFS). This paper derives an equivalent model for the ROM in a DDFS to analyze and reduce the access time that is critical to the performance of the DDFS. Moreover, the signal skew observed in the simulation waveform is illustrated. The proposed 64×3-bit ROM is integrated as a part of an 8-bit DDFS, which operates functionally at 6 GHz. Measurement results demonstrate the improvement in the spur free dynamic range. Direct digital frequency synthesizers (DDFS) are widely used in communication systems, chirp radar systems, and phase array antennas. To exploit DDFSs in broadband communication systems, DDFS designs operating at GHz-range clock frequencies are required. A direct digital synthesizer can be implemented from a phase accumulator, a phaseto-amplitude mapping block, and a digital-to-analog converter. The phase-to-amplitude mapping block is the key to a high performance DDFS. Many architectures and designs for the phase-to-amplitude mapping block in a DDFS have been reported in the literature. Phase-to-amplitude mapping methods are mainly based on ROM-based designs [1], computational mapping designs [2,3], or both [4-6]. The increasing demand for higher speed DDFS circuits and the frequency limitations in CMOS technologies have necessitated the development of DDFSs implemented using heterojunction bipolar transistor (HBT) technology. Although indium phosphide (InP) HBT based circuits tend to work at a high frequency, high cost and low yield have limited the development of InP HBT based large scale integrated (LSI) circuits. Gallium arsenide (GaAs) HBT combining high frequency and high yield with a moderate price, shows prominent application in mixed-signal integrated circuits with a high level of complexity, such as the ultrahigh speed DDFS with high spur free dynamic range (SFDR).Comparing to a DDFS with computational mapping [3], the one with both ROM and computational mapping [7] was found to have a higher SFDR. However, the ROM is often the limiting factor for the high speed of a DDFS, because it has to support clock rates in the order of two-and-half times the synthesized frequency [8]. Many technologies have been adopted to realize a high speed ROM with large size. The fastest CMOS ROM reported, operates at a frequency up to 1.1 GHz [9]. A 64-bit, 5-GHz read-write look-up table (LUT) has been implemented in GaAs HBT [10], while an InP HBT 36-GHz, 16×6-bit ROM test circuit has also been

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Section: Simulation Results and Discussionsupporting

confidence: 83%

Section: Simulation Results and Discussionmentioning

confidence: 99%

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A 6-GHz ROM suitable for DDFS application in GaAs HBT technology

Chen

Wang²,

et al. 2011

Chin. Sci. Bull.

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“…假设有 n 个存储单元与高位线相连, 则与低位线 [12] 或者二极管逻辑的与门 (AND gate) [8] . 列行 0 1 2 3 4 5 6 7 0 0 0 1 1 0 0 1 1 1 0 0 1 1 0 0 1 1 2 0 0 1 1 0 0 0 1 3 0 0 1 与本文观察到现象类似 , 当同一列的数据为 "1111111011111110", 未被选中存储单元的漏电流减少位线上电流幅度 , 寄生电容的充放电时间增加 [11] . 当输出序列为一长串"0"与少数"1", 或者相反 [1] InP HBT [11] CMOS [9] GaAs HBT [8] GaAs HBT [10] GaAs HBT (本文)…”

Section: 电路设计与分析unclassified

“…基于 CMOS 的只读存储器最高工作速度是 1.1 GHz [9] , 采用 GaAs HBT 工艺设计的 64 bit 查找表(look-up table, LUT)可工作在 5 GHz [10] . 基于 InP HBT 设计的 16×6 bit 只读存储器在 20 GHz 时输出达到 330 mV [11] , 而在 36 GHz 时下降到 160 mV.…”

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