36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security

Taneja, Sachin; Rajanna, Viveka Konandur; Alioto, Massimo

doi:10.1109/isscc42613.2021.9366019

Cited by 31 publications

(14 citation statements)

References 8 publications

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“…However, an analog/time to digital converter is necessary to digitize the entropy, increasing the area of the TRNG. The different kinds of Random Access Memory (RAM) are used to generate a random number, using the time response or leakage current [17]- [22]. Nevertheless, these entropy sources present the problem of characterizing the time response to obtain good digitization, and temperature variations affect the leakage current in RAM-TRNG or the additional mask for the resistive RAM.…”

Section: Introductionmentioning

confidence: 99%

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse

et al. 2022

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True Random Number Generator (TRNG) is used in many applications, generally for generating random cryptography keys. In this way, the trust of the cryptography system depends on the quality of the random numbers generated. However, the entropy fluctuations produced by external perturbations generate some false positives in the random sequence. These false positives can generate a disastrous scenario, depending on the application. This work presents the results of different tests to demonstrate the robustness and health of the TRNG based on frequency collapse. The TRNG passed all entropy tests provided for NIST SP800-90B and AIS31. The entropy test denotes a 0.9789 minimum entropy normalized and 7.998 Shannon entropy. In addition, the TRNG passes the health tests provided for NIST SP800-90B. The health test shows a number of identical values I v = 0%, I v−1 < 0.004% and a maximum cutoff value M C v = 10 with LM C v = 13 in the repetition count and adaptive proportion tests, respectively. The implementation passed all the statistical tests provided for NIST SP800-22 and AIS20. Besides, the implementation passes the different tests with Process, Voltage, and Temperature (PVT) variations. The TRNG is implemented in a 0.18µm General Purpose (GP) CMOS technology, occupying 25600µm 2 with four entropy sources. Finally, the implementation presents a 7.3 until 9.2-Mb/s of bit rate, 0.56 until 1.88-mW of power consumption, and 77.2 until 204.3-pJ/bit of energy per bit using an entropy source with 16 and 2 delay stages, respectively.

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Section: Introductionmentioning

confidence: 99%

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse

et al. 2022

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“…Metastability-based TRNGs are on the higher end of the throughput range [40], [51]- [56], although their advantage is becoming less pronounced over time due to the heavier effect of mismatch, and hence the number of raw bits to be post-processed to extract each output bit. Jitter- [22], [57]- [66] and chaotic map-based TRNGs [67]- [70] generally have lower throughput than metastability-based chaotic maps.…”

Section: B Trends and Advances In True Random Number Generatorsmentioning

confidence: 99%

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Alioto

2023

IEEE Open J. Solid-State Circuits Soc.

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This work presents an overview of challenges and solid pathways towards ubiquitous and sustainable hardware security in next-generation silicon chips at the edge of distributed and connected systems (e.g., IoT, AIoT). As first challenge, the increasingly connected nature and the exponential proliferation of edge devices is unabatingly increasing the overall attack surface, making attacks easier and mandating ubiquitous security down to each edge node. At the same time, the necessity to incorporate zero-trust policies in large-scale distributed systems requires a complete set of security primitives for hardware-backed authentication, and a higher degree of physical context awareness (including primitives detecting the onset of physical attacks). Thus, making the inclusion of such security primitives economically sustainable even in low-end devices is a second key challenge. As third challenge, the ever-changing vulnerability landscape and the need for increased chip longevity in distributed systems requires security assurance methods that are sustainable and adaptive across the entire chip lifecycle. In this work, design principles and promising directions to enable ubiquitous and sustainable security capabilities along with physical awareness are discussed. Such achievements require a fundamental rethinking of design methodologies to enable aggressive design and resource reuse (e.g., area, power, design effort), along with low-cost on-chip sensorization and intelligence for physical attack detection. Such rethinking inevitably crosses over the traditional design abstractions, and requires innovation from the physical to the algorithmic level. At the physical and circuit level, design and resource reuse is enabled by immersed-inlogic and in-memory security approaches. At the algorithm level, "hardware patching" is introduced and exemplified to show that run-time intelligence (machine learning) allows security capabilities to adapt and improve over time, as typical of security patching in software. Sensing techniques to detect attacks in situ from non-invasive to invasive are illustrated, while still preserving fully-automated design approaches. Overall, the above design principles are expected to push security capabilities in distributed systems to a new level, ultimately making the edge more intelligent and self-reliant, and security measures more distributed.

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“…This is related to a bi-stability of the SRAM memory cell, thus PUF output becomes more stable and unique code over the operating condition changes. By employing a temporal voting, an increasing entropy, or a discarding technique, a bit error rate (BER) can be enhanced by scarifying multiple cycle of computation time [17], scrambling PUF output [18,19], or masking out few SRAM bit cells [20]. Since the effectiveness of ECC is proportional to the complexity of the SRAM-based PUF associated with CRPs, it is important to have a higher number of CRPs.…”

Section: Introductionmentioning

confidence: 99%

Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique

2022

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This paper presents an ultra-small physical unclonable function (PUF) chip structure to protect data in compact IoT sensor devices. The proposed PUF has far fewer transistors and a reduced active area compared to the conventional strong PUF with multiple challenge response pairs (CRPs). According to the manufacturing process variations, the conventional SRAM-based PUF uses a switching transistor and a main transistor to implement multiple CRPs, whereas the proposed structure adds the function of a switching transistor to a single main transistor, controlling the body voltage to switch the transistor. For a PUF with a 32-bit challenge, the number of transistors is significantly reduced by 40%; the active area of the conventional structure is 57.78µm 2 while the area of the proposed structure is 36.4µm 2 . Overall, an active area reduction of 38% is realized with the same number of CRPs. Here, we implemented an SRAMbased PUF system with a 32-bit challenge, a 1024-bit response, and 160 million CRPs. PUF core cell shows energy efficiency of 0.09 pJ/bit. The inter-Hamming distance is 48.89%, while the intra-Hamming distance is 1.2% after data post-processing, i.e., discarding unstable bits. A prototype chip is implemented in the 65nm CMOS process with a supply voltage of 1.2V. Compared to the prior arts, the proposed prototype is shown effective silicon area reduction while maintaining remarkable energy efficiency.

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36.1 Unified In-Memory Dynamic TRNG and Multi-Bit Static PUF Entropy Generation for Ubiquitous Hardware Security

Cited by 31 publications

References 8 publications

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse

A Robust and Healthy Against PVT Variations TRNG Based on Frequency Collapse

Aggressive Design Reuse for Ubiquitous Zero-Trust Edge Security—From Physical Design to Machine-Learning-Based Hardware Patching

Compact SRAM-Based PUF Chip Employing Body Voltage Control Technique

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