350 mV, 0.5 mW, 5 GHz, 130 nm CMOS Class-C VCO Design Using Open Loop Analysis

Szczepkowski, Grzegorz; Farrell, Ronan

doi:10.1049/ic.2012.0184

Cited by 1 publication

(2 citation statements)

References 7 publications

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“…Figure 11 depicts the results of this comparison. The values in the range of better than -185 dBc/Hz are in line with FOMT levels for sub-1 V power supply CMOS VCO circuits reported in the literature [6], [8]- [12].…”

Section: B Power Consumption Tuning Range and Figure Of Merit Simulsupporting

confidence: 88%

“…The main source of this error comes from the placement of varactors at port P2 and introduction of additional set of amplitude dependant parasitics, distributed differently between the closed and open loop circuits. In our previous publication on 5 GHz class-C oscillator [6], varactors were placed at port P1, resulting in much closer results between SST and transient simulations, in the range of few percent. This shortcoming of high nonlinearity placement along the cascade has not been indicated previously by Randall and Hock [4].…”

Section: A Open Loop Transfer Function Analysismentioning

confidence: 88%

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Open loop approach to design low voltage, 400 mV, 1.3 mW, 10 GHz CMOS class-B VCO

Szczepkowski

Farrell

2012

2012 International Conference on Signals and Electronic Systems (ICSES)

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Abstract-The paper presents a method for design of LC cross-coupled oscillators based on an open loop technique and its practical application leading to a high frequency CMOS oscillator prototype. Thanks to the proposed approach, the main circuit parameters such as loaded quality factor (responsible for phase noise performance of LC oscillator) and steady-state oscillation amplitude, can be extracted without the necessity of time consuming transient simulations. The presented method is not technology specific and allows fast calculations under changing bias conditions. The proposed 130 nm CMOS prototype operates at 10 GHz from a 400m V power supply achieving an average SSB phase noise of -110 dBc/Hz at 1 MHz offset from the carrier and a fractional bandwidth of more than 7.5%. Low average power consumption of 1.3 mW RMS, has been obtained by biasing the oscillator devices to operate in class-B i.e. V GS = V DD = V th .

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Section: B Power Consumption Tuning Range and Figure Of Merit Simulsupporting

confidence: 88%

Section: A Open Loop Transfer Function Analysismentioning

confidence: 88%